Changes in directory llvm/lib/Target/PowerPC:
PPC.td updated: 1.17 -> 1.18
PPCISelLowering.cpp updated: 1.188 -> 1.189
PPCSubtarget.cpp updated: 1.20 -> 1.21
PPCSubtarget.h updated: 1.14 -> 1.15
---
Log message:
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
---
Diffs of the changes: (+12 -12)
PPC.td | 6 +++---
PPCISelLowering.cpp | 6 +++---
PPCSubtarget.cpp | 4 ++--
PPCSubtarget.h | 8 ++++----
4 files changed, 12 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC.td
diff -u llvm/lib/Target/PowerPC/PPC.td:1.17 llvm/lib/Target/PowerPC/PPC.td:1.18
--- llvm/lib/Target/PowerPC/PPC.td:1.17 Wed May 17 19:12:25 2006
+++ llvm/lib/Target/PowerPC/PPC.td Fri Jun 16 12:34:12 2006
@@ -19,10 +19,10 @@
// PowerPC Subtarget features.
//
-def Feature64Bit : SubtargetFeature<"64bit","Is64Bit", "true",
+def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
"Enable 64-bit instructions">;
-def Feature64BitRegs : SubtargetFeature<"64bitregs","Has64BitRegs", "true",
- "Enable 64-bit registers [beta]">;
+def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
+ "Enable 64-bit registers usage for ppc32
[beta]">;
def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
"Enable Altivec instructions">;
def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.188
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.189
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.188 Thu Jun 15 03:17:07 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jun 16 12:34:12 2006
@@ -146,7 +146,7 @@
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
- if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
+ if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
// They also have instructions for converting between i64 and fp.
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
@@ -163,7 +163,7 @@
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
}
- if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
+ if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
// 64 bit PowerPC implementations can support i64 types directly
addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
@@ -2227,7 +2227,7 @@
switch (N->getOpcode()) {
default: break;
case ISD::SINT_TO_FP:
- if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
+ if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
// Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without
load/stores.
// We allow the src/dst to be either f32/f64, but the intermediate
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
diff -u llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.20
llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.21
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.20 Thu Jun 15 20:37:27 2006
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp Fri Jun 16 12:34:12 2006
@@ -73,8 +73,8 @@
: StackAlignment(16)
, InstrItins()
, IsGigaProcessor(false)
- , Is64Bit(false)
- , Has64BitRegs(false)
+ , Has64BitSupport(false)
+ , Use64BitRegs(false)
, HasAltivec(false)
, HasFSQRT(false)
, HasSTFIWX(false)
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
diff -u llvm/lib/Target/PowerPC/PPCSubtarget.h:1.14
llvm/lib/Target/PowerPC/PPCSubtarget.h:1.15
--- llvm/lib/Target/PowerPC/PPCSubtarget.h:1.14 Thu Jun 15 20:37:27 2006
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h Fri Jun 16 12:34:12 2006
@@ -33,8 +33,8 @@
/// Used by the ISel to turn in optimizations for POWER4-derived
architectures
bool IsGigaProcessor;
- bool Is64Bit;
- bool Has64BitRegs;
+ bool Has64BitSupport;
+ bool Use64BitRegs;
bool HasAltivec;
bool HasFSQRT;
bool HasSTFIWX;
@@ -66,12 +66,12 @@
bool hasFSQRT() const { return HasFSQRT; }
bool hasSTFIWX() const { return HasSTFIWX; }
- bool has64BitRegs() const { return Has64BitRegs; }
+ bool use64BitRegs() const { return Use64BitRegs; }
bool hasAltivec() const { return HasAltivec; }
bool isAIX() const { return IsAIX; }
bool isDarwin() const { return IsDarwin; }
- bool is64Bit() const { return Is64Bit; }
+ bool has64BitSupport() const { return Has64BitSupport; }
bool isGigaProcessor() const { return IsGigaProcessor; }
};
} // End llvm namespace
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