Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.43 -> 1.44
AlphaISelLowering.cpp updated: 1.50 -> 1.51
AlphaISelLowering.h updated: 1.17 -> 1.18
---
Log message:
It really helps to be returning to the correct place
---
Diffs of the changes: (+17 -33)
AlphaISelDAGToDAG.cpp | 32 +++++---------------------------
AlphaISelLowering.cpp | 15 +++++++++------
AlphaISelLowering.h | 3 +++
3 files changed, 17 insertions(+), 33 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.43
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.44
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.43 Fri May 26 18:10:12 2006
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Tue Jun 13 13:27:39 2006
@@ -124,7 +124,7 @@
private:
SDOperand getGlobalBaseReg();
- SDOperand getRASaveReg();
+ SDOperand getGlobalRetAddr();
SDOperand SelectCALL(SDOperand Op);
};
@@ -141,7 +141,7 @@
/// getRASaveReg - Grab the return address
///
-SDOperand AlphaDAGToDAGISel::getRASaveReg() {
+SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
AlphaLowering.getVRegRA(),
MVT::i64);
@@ -197,6 +197,9 @@
case AlphaISD::GlobalBaseReg:
Result = getGlobalBaseReg();
return;
+ case AlphaISD::GlobalRetAddr:
+ Result = getGlobalRetAddr();
+ return;
case AlphaISD::DivCall: {
SDOperand Chain = CurDAG->getEntryNode();
@@ -226,30 +229,6 @@
return;
}
- case ISD::RET: {
- SDOperand Chain;
- Select(Chain, N->getOperand(0)); // Token chain.
- SDOperand InFlag(0,0);
-
- if (N->getNumOperands() == 3) {
- SDOperand Val;
- Select(Val, N->getOperand(1));
- if (N->getOperand(1).getValueType() == MVT::i64) {
- Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
- InFlag = Chain.getValue(1);
- } else if (N->getOperand(1).getValueType() == MVT::f64 ||
- N->getOperand(1).getValueType() == MVT::f32) {
- Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
- InFlag = Chain.getValue(1);
- }
- }
- Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
- InFlag = Chain.getValue(1);
-
- // Finally, select this to a ret instruction.
- Result = CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
- return;
- }
case ISD::Constant: {
uint64_t uval = cast<ConstantSDNode>(N)->getValue();
@@ -469,7 +448,6 @@
assert(0 && "Unknown operand");
}
-
// Finally, once everything is in registers to pass to the call, emit the
// call itself.
if (Addr.getOpcode() == AlphaISD::GPRelLo) {
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.50
llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.51
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.50 Mon Jun 12 13:09:24 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Tue Jun 13 13:27:39 2006
@@ -154,6 +154,7 @@
case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
case AlphaISD::RelLit: return "Alpha::RelLit";
case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
+ case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
case AlphaISD::CALL: return "Alpha::CALL";
case AlphaISD::DivCall: return "Alpha::DivCall";
case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
@@ -268,14 +269,17 @@
return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
}
-static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Copy;
+static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) {
+ SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
+ DAG.getNode(AlphaISD::GlobalRetAddr,
MVT::i64),
+ SDOperand());
switch (Op.getNumOperands()) {
default:
assert(0 && "Do not know how to return this many arguments!");
abort();
case 1:
- return SDOperand(); // ret void is legal
+ break;
+ //return SDOperand(); // ret void is legal
case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg;
@@ -285,8 +289,7 @@
assert(MVT::isFloatingPoint(ArgVT));
ArgReg = Alpha::F0;
}
- Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
- SDOperand());
+ Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
if(DAG.getMachineFunction().liveout_empty())
DAG.getMachineFunction().addLiveOut(ArgReg);
break;
@@ -384,7 +387,7 @@
VarArgsBase,
VarArgsOffset,
GP, RA);
- case ISD::RET: return LowerRET(Op,DAG);
+ case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
case ISD::SINT_TO_FP: {
assert(MVT::i64 == Op.getOperand(0).getValueType() &&
"Unhandled SINT_TO_FP type in custom expander!");
Index: llvm/lib/Target/Alpha/AlphaISelLowering.h
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.17
llvm/lib/Target/Alpha/AlphaISelLowering.h:1.18
--- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.17 Mon Jun 12 13:09:24 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.h Tue Jun 13 13:27:39 2006
@@ -37,6 +37,9 @@
/// GlobalBaseReg - used to restore the GOT ptr
GlobalBaseReg,
+
+ /// GlobalRetAddr - used to restore the return address
+ GlobalRetAddr,
/// CALL - Normal call.
CALL,
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
