Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.92 -> 1.93
---
Log message:
lib/Target/Target.td
---
Diffs of the changes: (+13 -12)
ScheduleDAG.cpp | 25 +++++++++++++------------
1 files changed, 13 insertions(+), 12 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.92
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.93
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.92 Tue May 16 01:10:57 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Thu May 18 15:42:07 2006
@@ -229,16 +229,17 @@
static unsigned CreateVirtualRegisters(MachineInstr *MI,
unsigned NumResults,
SSARegMap *RegMap,
+ const TargetInstrInfo *TII,
const TargetInstrDescriptor &II) {
// Create the result registers for this node and add the result regs to
// the machine instruction.
- const TargetOperandInfo *OpInfo = II.OpInfo;
- unsigned ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
+ unsigned ResultReg =
+ RegMap->createVirtualRegister(TII->getInstrOperandRegClass(&II, 0));
MI->addRegOperand(ResultReg, MachineOperand::Def);
for (unsigned i = 1; i != NumResults; ++i) {
- assert(OpInfo[i].RegClass && "Isn't a register operand!");
- MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass),
- MachineOperand::Def);
+ const TargetRegisterClass *RC = TII->getInstrOperandRegClass(&II, i);
+ assert(RC && "Isn't a register operand!");
+ MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def);
}
return ResultReg;
}
@@ -275,9 +276,9 @@
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
- assert(II->OpInfo[IIOpNum].RegClass &&
- "Don't have operand info for this instruction!");
- assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass &&
+ const TargetRegisterClass *RC = TII->getInstrOperandRegClass(II,
IIOpNum);
+ assert(RC && "Don't have operand info for this instruction!");
+ assert(RegMap->getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
}
} else if (ConstantSDNode *C =
@@ -332,9 +333,9 @@
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
- assert(II->OpInfo[IIOpNum].RegClass &&
- "Don't have operand info for this instruction!");
- assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass &&
+ const TargetRegisterClass *RC = TII->getInstrOperandRegClass(II,
IIOpNum);
+ assert(RC && "Don't have operand info for this instruction!");
+ assert(RegMap->getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
}
}
@@ -387,7 +388,7 @@
// Otherwise, create new virtual registers.
if (NumResults && VRBase == 0)
- VRBase = CreateVirtualRegisters(MI, NumResults, RegMap, II);
+ VRBase = CreateVirtualRegisters(MI, NumResults, RegMap, TII, II);
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
