[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.165 -> 1.166
---
Log message:

Make the case I just checked in stronger.  Now we compile this:

short test2(short X, short x) {
  int Y = (short)(X+x);
  return Y >> 1;
}

to:

_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r3, r2, 1
        blr

instead of:

_test2:
        add r2, r3, r4
        extsh r2, r2
        srwi r2, r2, 1
        extsh r3, r2
        blr



---
Diffs of the changes:  (+13 -5)

 DAGCombiner.cpp |   18 +++++++++++++-----
 1 files changed, 13 insertions(+), 5 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.165 
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.166
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.165 Mon May  8 15:59:41 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp       Mon May  8 16:18:59 2006
@@ -1948,17 +1948,25 @@
       EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
     return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
   }
+
+  // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
+  if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
+    return DAG.getZeroExtendInReg(N0, EVT);
   
   // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
+  // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
+  // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
   if (N0.getOpcode() == ISD::SRL) {
     if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
-      if (ShAmt->getValue()+EVTBits == MVT::getSizeInBits(VT))
-        return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
+      if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
+        // We can turn this into an SRA iff the input to the SRL is already 
sign
+        // extended enough.
+        unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
+        if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
+          return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
+      }
   }
   
-  // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
-  if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
-    return DAG.getZeroExtendInReg(N0, EVT);
   // fold (sext_inreg (extload x)) -> (sextload x)
   if (N0.getOpcode() == ISD::EXTLOAD && 
       EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&



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