[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.153 -> 1.154
---
Log message:

Pull and through and/or/xor.  This compiles some bitfield code to:

        mov EAX, DWORD PTR [ESP + 4]
        mov ECX, DWORD PTR [EAX]
        mov EDX, ECX
        add EDX, EDX
        or EDX, ECX
        and EDX, -2147483648
        and ECX, 2147483647
        or EDX, ECX
        mov DWORD PTR [EAX], EDX
        ret

instead of:

        sub ESP, 4
        mov DWORD PTR [ESP], ESI
        mov EAX, DWORD PTR [ESP + 8]
        mov ECX, DWORD PTR [EAX]
        mov EDX, ECX
        add EDX, EDX
        mov ESI, ECX
        and ESI, -2147483648
        and EDX, -2147483648
        or EDX, ESI
        and ECX, 2147483647
        or EDX, ECX
        mov DWORD PTR [EAX], EDX
        mov ESI, DWORD PTR [ESP]
        add ESP, 4
        ret



---
Diffs of the changes:  (+6 -4)

 DAGCombiner.cpp |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.153 
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.154
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.153 Fri May  5 00:58:59 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp       Fri May  5 01:10:43 2006
@@ -1069,11 +1069,13 @@
     return DAG.getNode(ISD::TRUNCATE, VT, ORNode);
   }
   
-  // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
-  // fold (or  (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or  x, y))
-  // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y))
+  
+  // For each of OP in SHL/SRL/SRA/AND...
+  //   fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
+  //   fold (or  (OP x, z), (OP y, z)) -> (OP (or  x, y), z)
+  //   fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
   if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
-       N0.getOpcode() == ISD::SRA) &&
+       N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
       N0.getOperand(1) == N1.getOperand(1)) {
     SDOperand ORNode = DAG.getNode(N->getOpcode(),
                                    N0.getOperand(0).getValueType(),



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