Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.86 -> 1.87
---
Log message:
psll*, psrl*, and psra* intrinsics.
---
Diffs of the changes: (+99 -1)
X86InstrSSE.td | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 99 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.86
llvm/lib/Target/X86/X86InstrSSE.td:1.87
--- llvm/lib/Target/X86/X86InstrSSE.td:1.86 Thu Apr 13 13:11:28 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 13 19:14:05 2006
@@ -1522,10 +1522,108 @@
}
let isTwoAddress = 1 in {
+def PSLLWrr : PDIi8<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+ "psllw {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
+ VR128:$src2))]>;
+def PSLLWrm : PDIi8<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ "psllw {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2))))]>;
+def PSLLWri : PDIi8<0x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+ "psllw {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2))))]>;
+def PSLLDrr : PDIi8<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+ "pslld {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
+ VR128:$src2))]>;
+def PSLLDrm : PDIi8<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ "pslld {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2))))]>;
+def PSLLDri : PDIi8<0x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+ "pslld {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2))))]>;
+def PSLLQrr : PDIi8<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+ "psllq {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
+ VR128:$src2))]>;
+def PSLLQrm : PDIi8<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ "psllq {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2))))]>;
+def PSLLQri : PDIi8<0x73, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+ "psllq {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2))))]>;
def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1,
i32i8imm:$src2),
"pslldq {$src2, $dst|$dst, $src2}", []>;
-def PSRLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1,
i32i8imm:$src2),
+
+def PSRLWrr : PDIi8<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+ "psrlw {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
+ VR128:$src2))]>;
+def PSRLWrm : PDIi8<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ "psrlw {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2))))]>;
+def PSRLWri : PDIi8<0x71, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+ "psrlw {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2))))]>;
+def PSRLDrr : PDIi8<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+ "psrld {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
+ VR128:$src2))]>;
+def PSRLDrm : PDIi8<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ "psrld {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2))))]>;
+def PSRLDri : PDIi8<0x72, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+ "psrld {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2))))]>;
+def PSRLQrr : PDIi8<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+ "psrlq {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
+ VR128:$src2))]>;
+def PSRLQrm : PDIi8<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ "psrlq {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2))))]>;
+def PSRLQri : PDIi8<0x73, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+ "psrlq {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2))))]>;
+def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1,
i32i8imm:$src2),
"psrldq {$src2, $dst|$dst, $src2}", []>;
+
+def PSRAWrr : PDIi8<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+ "psraw {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
+ VR128:$src2))]>;
+def PSRAWrm : PDIi8<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ "psraw {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2))))]>;
+def PSRAWri : PDIi8<0x71, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+ "psraw {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2))))]>;
+def PSRADrr : PDIi8<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+ "psrad {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
+ VR128:$src2))]>;
+def PSRADrm : PDIi8<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ "psrad {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2))))]>;
+def PSRADri : PDIi8<0x72, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+ "psrad {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2))))]>;
}
// Logical
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