Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.146 -> 1.147
LegalizeDAG.cpp updated: 1.355 -> 1.356
---
Log message:
Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patterns
to match again :)
---
Diffs of the changes: (+50 -2)
DAGCombiner.cpp | 36 ++++++++++++++++++++++++++++++++++++
LegalizeDAG.cpp | 16 ++++++++++++++--
2 files changed, 50 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.146
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.147
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.146 Fri Apr 7 23:15:24 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Apr 8 00:34:25 2006
@@ -2735,6 +2735,42 @@
}
if (isIdentity) return N->getOperand(1);
+ // If the LHS and the RHS are the same node, turn the RHS into an undef.
+ if (N->getOperand(0) == N->getOperand(1)) {
+ // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
+ // first operand.
+ std::vector<SDOperand> MappedOps;
+ for (unsigned i = 0; i != NumElts; ++i) {
+ if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
+ cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
+ MappedOps.push_back(ShufMask.getOperand(i));
+ } else {
+ unsigned NewIdx =
+ cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
+ MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
+ }
+ }
+ // Add the type/#elts values.
+ MappedOps.push_back(ShufMask.getOperand(NumElts));
+ MappedOps.push_back(ShufMask.getOperand(NumElts+1));
+
+ ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
+ MappedOps);
+ AddToWorkList(ShufMask.Val);
+
+ // Build the undef vector.
+ SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
+ for (unsigned i = 0; i != NumElts; ++i)
+ MappedOps[i] = UDVal;
+ MappedOps[NumElts ] = *(N->getOperand(0).Val->op_end()-2);
+ MappedOps[NumElts+1] = *(N->getOperand(0).Val->op_end()-1);
+ UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps);
+
+ return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
+ N->getOperand(0), UDVal, ShufMask,
+ MappedOps[NumElts], MappedOps[NumElts+1]);
+ }
+
return SDOperand();
}
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.355
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.356
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.355 Fri Apr 7 23:13:17 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Apr 8 00:34:25 2006
@@ -4697,8 +4697,20 @@
Result = Node->getOperand(0);
} else {
// Returning a BUILD_VECTOR?
- std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
- Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
+
+ // If all elements of the build_vector are undefs, return an undef.
+ bool AllUndef = true;
+ for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
+ if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
+ AllUndef = false;
+ break;
+ }
+ if (AllUndef) {
+ Result = DAG.getNode(ISD::UNDEF, NewVT);
+ } else {
+ std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
+ Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
+ }
}
break;
case ISD::VINSERT_VECTOR_ELT:
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