Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.40 -> 1.41
PPCInstrFormats.td updated: 1.72 -> 1.73
README_ALTIVEC.txt updated: 1.14 -> 1.15
---
Log message:
Add all of the data stream intrinsics and instructions. woo
---
Diffs of the changes: (+43 -7)
PPCInstrAltivec.td | 21 +++++++++++++++++++++
PPCInstrFormats.td | 22 ++++++++++++++++++++++
README_ALTIVEC.txt | 7 -------
3 files changed, 43 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.40
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.41
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.40 Wed Apr 5 15:15:25 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Wed Apr 5 17:27:14 2006
@@ -93,6 +93,15 @@
def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
[(set VRRC:$rD, (v4f32 (undef)))]>;
+let noResults = 1 in {
+def DSS : DSS_Form<822, (ops u5imm:$A,
u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
+ "dss $STRM, $A", LdStGeneral /*FIXME*/, []>;
+def DST : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
+ "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
+def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
+ "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
+}
+
def MFVSCR : VXForm_4<1540, (ops VRRC:$vD),
"mfvcr $vD", LdStGeneral,
[(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>;
@@ -431,6 +440,18 @@
// Additional Altivec Patterns
//
+// DS* intrinsics.
+def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
+def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>;
+def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
+ (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
+def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM),
+ (DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
+def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM),
+ (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
+def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
+ (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
+
// Undef/Zero.
def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.72
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.73
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.72 Tue Apr 4 19:03:57 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Wed Apr 5 17:27:14 2006
@@ -325,6 +325,26 @@
: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
}
+// DSS_Form - Form X instruction, used for altivec dss* instructions.
+class DSS_Form<bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<31, OL, asmstr, itin> {
+ bits<1> T;
+ bits<2> STRM;
+ bits<5> A;
+ bits<5> B;
+
+ let Pattern = pattern;
+
+ let Inst{6} = T;
+ let Inst{7-8} = 0;
+ let Inst{9-10} = STRM;
+ let Inst{11-15} = A;
+ let Inst{16-20} = B;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
// 1.7.7 XL-Form
class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
InstrItinClass itin>
@@ -589,6 +609,8 @@
let Inst{31} = RC;
}
+
+
// E-1 VA-Form
// VAForm_1 - DACB ordering.
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.14
llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.15
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.14 Tue Apr 4 19:49:48 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Wed Apr 5 17:27:14 2006
@@ -47,13 +47,6 @@
//===----------------------------------------------------------------------===//
-Missing intrinsics:
-
-ds*
-vsel (some aliases only accessible using builtins)
-
-//===----------------------------------------------------------------------===//
-
FABS/FNEG can be codegen'd with the appropriate and/xor of -0.0.
//===----------------------------------------------------------------------===//
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