Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.116 -> 1.117
PPCISelLowering.h updated: 1.35 -> 1.36
PPCInstrAltivec.td updated: 1.14 -> 1.15
PPCInstrInfo.td updated: 1.212 -> 1.213
---
Log message:
Use normal lvx for scalar_to_vector instead of lve*x. They do the exact
same thing and we have a dag node for the former.
---
Diffs of the changes: (+5 -20)
PPCISelLowering.cpp | 6 ++----
PPCISelLowering.h | 8 --------
PPCInstrAltivec.td | 10 +++-------
PPCInstrInfo.td | 1 -
4 files changed, 5 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.116
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.117
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.116 Mon Mar 27 18:40:33 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 27 19:43:22 2006
@@ -222,7 +222,6 @@
case PPCISD::STFIWX: return "PPCISD::STFIWX";
case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
- case PPCISD::LVE_X: return "PPCISD::LVE_X";
case PPCISD::VPERM: return "PPCISD::VPERM";
case PPCISD::Hi: return "PPCISD::Hi";
case PPCISD::Lo: return "PPCISD::Lo";
@@ -697,9 +696,8 @@
// Store the input value into Value#0 of the stack slot.
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
Op.getOperand(0),
FIdx,DAG.getSrcValue(NULL));
- // LVE_X it out.
- return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx,
- DAG.getSrcValue(NULL));
+ // Load it out.
+ return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
}
case ISD::BUILD_VECTOR:
// If this is a case we can't handle, return null and let the default
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.35
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.36
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.35 Sun Mar 26 04:06:40 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Mon Mar 27 19:43:22 2006
@@ -48,14 +48,6 @@
// three v4f32 operands and producing a v4f32 result.
VMADDFP, VNMSUBFP,
- /// LVE_X - The PPC LVE*X instructions. The size of the element loaded
is
- /// the size of the element type of the vector result. The element
loaded
- /// depends on the alignment of the input pointer.
- ///
- /// The first operand is a token chain, the second is the address to load
- /// the third is the SRCVALUE node.
- LVE_X,
-
/// VPERM - The PPC VPERM Instruction.
///
VPERM,
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.14
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.15
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.14 Mon Mar 27 18:40:33 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Mon Mar 27 19:43:22 2006
@@ -69,13 +69,13 @@
let isLoad = 1, PPC970_Unit = 2 in { // Loads.
def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
"lvebx $vD, $src", LdStGeneral,
- [(set VRRC:$vD, (v16i8 (PPClve_x xoaddr:$src)))]>;
+ []>;
def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
"lvehx $vD, $src", LdStGeneral,
- [(set VRRC:$vD, (v8i16 (PPClve_x xoaddr:$src)))]>;
+ []>;
def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
"lvewx $vD, $src", LdStGeneral,
- [(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
+ []>;
def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
"lvx $vD, $src", LdStGeneral,
[(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
@@ -511,7 +511,3 @@
def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
(v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
-def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
- (v4i32 (LVEWX xoaddr:$src))>;
-
-
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.212
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.213
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.212 Sun Mar 26 04:06:40 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 27 19:43:22 2006
@@ -53,7 +53,6 @@
def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
-def PPClve_x : SDNode<"PPCISD::LVE_X", SDTLoad, [SDNPHasChain]>;
def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
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