[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstrAltivec.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.115 -> 1.116
PPCInstrAltivec.td updated: 1.13 -> 1.14
---
Log message:

Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum 
value.  Split them into separate enums.


---
Diffs of the changes:  (+11 -11)

 PPCISelLowering.cpp |    4 ++--
 PPCInstrAltivec.td  |   18 +++++++++---------
 2 files changed, 11 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.115 
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.116
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.115   Sun Mar 26 19:32:24 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 27 18:40:33 2006
@@ -138,7 +138,7 @@
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Expand);
   
   // We want to custom lower some of our intrinsics.
-  setOperationAction(ISD::INTRINSIC         , MVT::Other, Custom);
+  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
   
   if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
     // They also have instructions for converting between i64 and fp.
@@ -752,7 +752,7 @@
     SDOperand VPermMask =DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 
ResultMask);
     return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
   }
-  case ISD::INTRINSIC: {
+  case ISD::INTRINSIC_WO_CHAIN: {
     bool HasChain = Op.getOperand(0).getValueType() == MVT::Other;
     unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(HasChain))->getValue();
     


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.13 
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.14
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.13     Sun Mar 26 21:34:17 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td  Mon Mar 27 18:40:33 2006
@@ -89,15 +89,15 @@
                    []>, PPC970_Unit_LSU;
 
 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {   // Stores.
-def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
-                   "stvebx $rS, $rA, $rB", LdStGeneral,
-                   []>;
-def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
-                   "stvehx $rS, $rA, $rB", LdStGeneral,
-                   []>;
-def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
-                   "stvewx $rS, $rA, $rB", LdStGeneral,
-                   []>;
+def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
+                   "stvebx $rS, $dst", LdStGeneral,
+                   [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
+def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
+                   "stvehx $rS, $dst", LdStGeneral,
+                   [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
+def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
+                   "stvewx $rS, $dst", LdStGeneral,
+                   [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
 def STVX  : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
                    "stvx $rS, $dst", LdStGeneral,
                    [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;



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