Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.11 -> 1.12
PPCInstrFormats.td updated: 1.69 -> 1.70
---
Log message:
Fix the JIT encoding of VSPLTI*
---
Diffs of the changes: (+24 -9)
PPCInstrAltivec.td | 18 +++++++++---------
PPCInstrFormats.td | 15 +++++++++++++++
2 files changed, 24 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.11
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.12
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.11 Sun Mar 26 16:38:43 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sun Mar 26 21:28:57 2006
@@ -290,15 +290,15 @@
[(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB),
(undef),
VSPLT_shuffle_mask:$UIMM))]>;
-def VSPLTISB : VXForm_1<780, (ops VRRC:$vD, s5imm:$SIMM),
- "vspltisb $vD, $SIMM", VecPerm,
- [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
-def VSPLTISH : VXForm_1<844, (ops VRRC:$vD, s5imm:$SIMM),
- "vspltish $vD, $SIMM", VecPerm,
- [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
-def VSPLTISW : VXForm_1<908, (ops VRRC:$vD, s5imm:$SIMM),
- "vspltisw $vD, $SIMM", VecPerm,
- [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
+def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
+ "vspltisb $vD, $SIMM", VecPerm,
+ [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
+def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
+ "vspltish $vD, $SIMM", VecPerm,
+ [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
+def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
+ "vspltisw $vD, $SIMM", VecPerm,
+ [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
// Altivec Comparisons.
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.69
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.70
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.69 Sat Mar 25 22:57:17 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Sun Mar 26 21:28:57 2006
@@ -663,6 +663,21 @@
let Inst{21-31} = xo;
}
+class VXForm_3<bits<11> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<4, OL, asmstr, itin> {
+ bits<5> VD;
+ bits<5> IMM;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = IMM;
+ let Inst{16-20} = 0;
+ let Inst{21-31} = xo;
+}
+
+
// E-4 VXR-Form
class VXRForm_1<bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>
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