Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.111 -> 1.112
PPCInstrInfo.td updated: 1.209 -> 1.210
---
Log message:
Add some basic patterns for other datatypes
---
Diffs of the changes: (+12 -10)
PPCISelLowering.cpp | 6 ++----
PPCInstrInfo.td | 16 ++++++++++------
2 files changed, 12 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.111
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.112
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.111 Sat Mar 25 00:12:06 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Mar 25 01:39:07 2006
@@ -172,7 +172,6 @@
setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
- setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
@@ -181,14 +180,13 @@
if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
+ addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
+ addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
setOperationAction(ISD::ADD , MVT::v4f32, Legal);
setOperationAction(ISD::SUB , MVT::v4f32, Legal);
setOperationAction(ISD::MUL , MVT::v4f32, Legal);
- setOperationAction(ISD::LOAD , MVT::v4f32, Legal);
setOperationAction(ISD::ADD , MVT::v4i32, Legal);
- setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
- setOperationAction(ISD::LOAD , MVT::v16i8, Legal);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.209
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.210
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.209 Sat Mar 25 01:05:55 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Sat Mar 25 01:39:07 2006
@@ -513,10 +513,10 @@
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
"lvebx $vD, $src", LdStGeneral,
- []>;
+ [(set VRRC:$vD, (v16i8 (PPClve_x xoaddr:$src)))]>;
def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
"lvehx $vD, $src", LdStGeneral,
- []>;
+ [(set VRRC:$vD, (v8i16 (PPClve_x xoaddr:$src)))]>;
def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
"lvewx $vD, $src", LdStGeneral,
[(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
@@ -1244,10 +1244,9 @@
def : Pat<(f64 (extload xaddr:$src, f32)),
(FMRSD (LFSX xaddr:$src))>;
-def : Pat<(v4i32 (load xoaddr:$src)),
- (v4i32 (LVX xoaddr:$src))>;
-def : Pat<(v16i8 (load xoaddr:$src)),
- (v16i8 (LVX xoaddr:$src))>;
+def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
+def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
+def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
@@ -1256,8 +1255,13 @@
def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
(v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
+def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
+ (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
+def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
+ (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
+
def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
(v4i32 (LVEWX xoaddr:$src))>;
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
