Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.108 -> 1.109
PPCISelLowering.h updated: 1.31 -> 1.32
PPCInstrInfo.td updated: 1.205 -> 1.206
---
Log message:
add support for using vxor to build zero vectors. This implements
Regression/CodeGen/PowerPC/vec_zero.ll
---
Diffs of the changes: (+44 -4)
PPCISelLowering.cpp | 36 +++++++++++++++++++++++++++++++++---
PPCISelLowering.h | 4 ++++
PPCInstrInfo.td | 8 +++++++-
3 files changed, 44 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.108
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.109
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.108 Tue Mar 21 23:30:33 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Mar 24 01:48:08 2006
@@ -170,9 +170,6 @@
setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
-
- // FIXME: We don't support any BUILD_VECTOR's yet. We should custom expand
- // the ones we do, like splat(0.0) and splat(-0.0).
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
}
@@ -193,6 +190,9 @@
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
+
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
}
setSetCCResultContents(ZeroOrOneSetCCResult);
@@ -276,6 +276,26 @@
return cast<ConstantSDNode>(N->getOperand(0))->getValue();
}
+/// isZeroVector - Return true if this build_vector is an all-zero vector.
+///
+bool PPC::isZeroVector(SDNode *N) {
+ if (MVT::isInteger(N->getOperand(0).getValueType())) {
+ for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+ if (!isa<ConstantSDNode>(N->getOperand(i)) ||
+ cast<ConstantSDNode>(N->getOperand(i))->getValue() != 0)
+ return false;
+ } else {
+ assert(MVT::isFloatingPoint(N->getOperand(0).getValueType()) &&
+ "Vector of non-int, non-float values?");
+ // See if this is all zeros.
+ for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+ if (!isa<ConstantFPSDNode>(N->getOperand(i)) ||
+ !cast<ConstantFPSDNode>(N->getOperand(i))->isExactlyValue(0.0))
+ return false;
+ }
+ return true;
+}
+
/// LowerOperation - Provide custom lowering hooks for some operations.
///
@@ -634,6 +654,16 @@
return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx,
DAG.getSrcValue(NULL));
}
+ case ISD::BUILD_VECTOR:
+ // If this is a case we can't handle, return null and let the default
+ // expansion code take care of it. If we CAN select this case, return Op.
+
+ // See if this is all zeros.
+ // FIXME: We should handle splat(-0.0), and other cases here.
+ if (PPC::isZeroVector(Op.Val))
+ return Op;
+ return SDOperand();
+
case ISD::VECTOR_SHUFFLE: {
SDOperand V1 = Op.getOperand(0);
SDOperand V2 = Op.getOperand(1);
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.31
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.32
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.31 Tue Mar 21 23:30:33 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Fri Mar 24 01:48:08 2006
@@ -101,6 +101,10 @@
/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat
the
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned getVSPLTImmediate(SDNode *N);
+
+ /// isZeroVector - Return true if this build_vector is an all-zero vector.
+ ///
+ bool isZeroVector(SDNode *N);
}
class PPCTargetLowering : public TargetLowering {
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.205
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.206
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.205 Fri Mar 24 01:12:19 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Fri Mar 24 01:48:08 2006
@@ -135,6 +135,11 @@
return PPC::isSplatShuffleMask(N);
}], VSPLT_get_imm>;
+def vecimm0 : PatLeaf<(build_vector), [{
+ return PPC::isZeroVector(N);
+}]>;
+
+
//===----------------------------------------------------------------------===//
// PowerPC Flag Definitions.
@@ -1061,7 +1066,7 @@
def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
"vxor $vD, $vD, $vD", VecFP,
- []>;
+ [(set VRRC:$vD, (v4f32 vecimm0))]>;
}
@@ -1209,6 +1214,7 @@
(v4i32 (LVEWX xoaddr:$src))>;
def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
+def : Pat<(v4i32 vecimm0), (v4i32 (V_SET0))>;
// bit_convert
def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
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