Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.330 -> 1.331
---
Log message:
Endianness does not affect the order of vector fields. This fixes
SingleSource/UnitTests/Vector/build.c
---
Diffs of the changes: (+1 -6)
LegalizeDAG.cpp | 7 +------
1 files changed, 1 insertion(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.330
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.331
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.330 Tue Mar 21 18:12:37 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 21 19:46:54 2006
@@ -3155,7 +3155,6 @@
// Emit a store of each element to the stack slot.
std::vector<SDOperand> Stores;
- bool isLittleEndian = TLI.isLittleEndian();
unsigned TypeByteSize =
MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
unsigned VectorSize = MVT::getSizeInBits(VT)/8;
@@ -3164,11 +3163,7 @@
// Ignore undef elements.
if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
- unsigned Offset;
- if (isLittleEndian)
- Offset = TypeByteSize*i;
- else
- Offset = TypeByteSize*(e-i-1);
+ unsigned Offset = TypeByteSize*i;
SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
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