Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.311 -> 1.312
ScheduleDAGList.cpp updated: 1.21 -> 1.22
---
Log message:
remove "Slot", it is dead
---
Diffs of the changes: (+56 -34)
LegalizeDAG.cpp | 27 ++++++++++++++++++++--
ScheduleDAGList.cpp | 63 +++++++++++++++++++++++++---------------------------
2 files changed, 56 insertions(+), 34 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.311
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.312
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.311 Sat Mar 4 23:09:38 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 7 22:37:58 2006
@@ -1795,10 +1795,33 @@
case TargetLowering::Custom:
Tmp1 = TLI.LowerOperation(Result, DAG);
if (Tmp1.Val) Result = Tmp1;
- break;
+ break;
case TargetLowering::Legal: break;
case TargetLowering::Expand:
- // Floating point mod -> fmod libcall.
+ // If this target supports fabs/fneg natively, do this efficiently.
+ if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
+ TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
+ // Get the sign bit of the RHS.
+ MVT::ValueType IVT =
+ Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
+ SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
+ SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
+ SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
+ // Get the absolute value of the result.
+ SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
+ // Select between the nabs and abs value based on the sign bit of
+ // the input.
+ Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
+ DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
+ AbsVal),
+ AbsVal);
+ Result = LegalizeOp(Result);
+ break;
+ }
+
+ // Otherwise, do bitwise ops!
+
+ // copysign -> copysignf/copysign libcall.
const char *FnName;
if (Node->getValueType(0) == MVT::f32) {
FnName = "copysignf";
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.21
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.22
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.21 Tue Mar 7
22:25:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Tue Mar 7 22:37:58 2006
@@ -20,7 +20,6 @@
#define DEBUG_TYPE "sched"
#include "llvm/CodeGen/ScheduleDAG.h"
-#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
@@ -36,36 +35,36 @@
Statistic<> NumNoops ("scheduler", "Number of noops inserted");
Statistic<> NumStalls("scheduler", "Number of pipeline stalls");
-/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or a
-/// group of nodes flagged together.
-struct SUnit {
- SDNode *Node; // Representative node.
- std::vector<SDNode*> FlaggedNodes; // All nodes flagged to Node.
- std::set<SUnit*> Preds; // All real predecessors.
- std::set<SUnit*> ChainPreds; // All chain predecessors.
- std::set<SUnit*> Succs; // All real successors.
- std::set<SUnit*> ChainSuccs; // All chain successors.
- int NumPredsLeft; // # of preds not scheduled.
- int NumSuccsLeft; // # of succs not scheduled.
- int NumChainPredsLeft; // # of chain preds not scheduled.
- int NumChainSuccsLeft; // # of chain succs not scheduled.
- int SethiUllman; // Sethi Ullman number.
- bool isTwoAddress; // Is a two-address instruction.
- bool isDefNUseOperand; // Is a def&use operand.
- unsigned Latency; // Node latency.
- unsigned CycleBound; // Upper/lower cycle to be scheduled at.
- unsigned Slot; // Cycle node is scheduled at.
- SUnit *Next;
-
- SUnit(SDNode *node)
- : Node(node), NumPredsLeft(0), NumSuccsLeft(0),
+ /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode
or a
+ /// group of nodes flagged together.
+ struct SUnit {
+ SDNode *Node; // Representative node.
+ std::vector<SDNode*> FlaggedNodes; // All nodes flagged to Node.
+ std::set<SUnit*> Preds; // All real predecessors.
+ std::set<SUnit*> ChainPreds; // All chain predecessors.
+ std::set<SUnit*> Succs; // All real successors.
+ std::set<SUnit*> ChainSuccs; // All chain successors.
+ int NumPredsLeft; // # of preds not scheduled.
+ int NumSuccsLeft; // # of succs not scheduled.
+ int NumChainPredsLeft; // # of chain preds not scheduled.
+ int NumChainSuccsLeft; // # of chain succs not scheduled.
+ int SethiUllman; // Sethi Ullman number.
+ bool isTwoAddress; // Is a two-address instruction.
+ bool isDefNUseOperand; // Is a def&use operand.
+ unsigned Latency; // Node latency.
+ unsigned CycleBound; // Upper/lower cycle to be scheduled
at.
+ SUnit *Next;
+
+ SUnit(SDNode *node)
+ : Node(node), NumPredsLeft(0), NumSuccsLeft(0),
NumChainPredsLeft(0), NumChainSuccsLeft(0),
SethiUllman(INT_MIN),
isTwoAddress(false), isDefNUseOperand(false),
- Latency(0), CycleBound(0), Slot(0), Next(NULL) {}
-
- void dump(const SelectionDAG *G, bool All=true) const;
-};
+ Latency(0), CycleBound(0), Next(NULL) {}
+
+ void dump(const SelectionDAG *G, bool All=true) const;
+ };
+}
void SUnit::dump(const SelectionDAG *G, bool All) const {
std::cerr << "SU: ";
@@ -122,6 +121,7 @@
}
}
+namespace {
/// Sorting functions for the Available queue.
struct ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
bool operator()(const SUnit* left, const SUnit* right) const {
@@ -159,8 +159,10 @@
return false;
}
};
+} // end anonymous namespace
+namespace {
/// ScheduleDAGList - List scheduler.
class ScheduleDAGList : public ScheduleDAG {
private:
@@ -219,7 +221,7 @@
void BuildSchedUnits();
void EmitSchedule();
};
-} // end namespace
+} // end anonymous namespace
HazardRecognizer::~HazardRecognizer() {}
@@ -305,7 +307,6 @@
DEBUG(SU->dump(&DAG, false));
Sequence.push_back(SU);
- SU->Slot = CurrCycle;
// Bottom up: release predecessors
for (std::set<SUnit*>::iterator I1 = SU->Preds.begin(),
@@ -329,7 +330,6 @@
DEBUG(SU->dump(&DAG, false));
Sequence.push_back(SU);
- SU->Slot = CurrCycle;
// Bottom up: release successors.
for (std::set<SUnit*>::iterator I1 = SU->Succs.begin(),
@@ -384,7 +384,6 @@
// Add entry node last
if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
- Entry->Slot = CurrCycle;
Sequence.push_back(Entry);
}
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