Changes in directory llvm/lib/Target/PowerPC:
PPCHazardRecognizers.cpp updated: 1.1 -> 1.2
---
Log message:
add some comments that describe what we model
---
Diffs of the changes: (+18 -3)
PPCHazardRecognizers.cpp | 21 ++++++++++++++++++---
1 files changed, 18 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
diff -u llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.1
llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.2
--- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.1 Tue Mar 7
00:32:48 2006
+++ llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp Tue Mar 7 00:44:19 2006
@@ -22,6 +22,24 @@
//===----------------------------------------------------------------------===//
// PowerPC 970 Hazard Recognizer
//
+// This models the dispatch group formation of the PPC970 processor. Dispatch
+// groups are bundles of up to five instructions that can contain up to two ALU
+// (aka FXU) ops, two FPU ops, two Load/Store ops, one CR op, one VALU op, one
+// VPERM op, and one BRANCH op. If the code contains more instructions in a
+// sequence than the dispatch group can contain (e.g. three loads in a row) the
+// processor terminates the dispatch group early, wasting execution resources.
+//
+// In addition to these restrictions, there are a number of other restrictions:
+// some instructions, e.g. branches, are required to be the last instruction in
+// a group. Additionally, only branches can issue in the 5th (last) slot.
+//
+// Finally, there are a number of "structural" hazards on the PPC970. These
+// conditions cause large performance penalties due to misprediction, recovery,
+// and replay logic that has to happen. These cases include setting a CTR and
+// branching through it in the same dispatch group, and storing to an address,
+// then loading from the same address within a dispatch group. To avoid these
+// conditions, we insert no-op instructions when appropriate.
+//
// FIXME: This is missing some significant cases:
// 0. Handling of instructions that must be the first/last in a group.
// 1. Modeling of microcoded instructions.
@@ -30,9 +48,6 @@
// 4. Handling of the esoteric cases in "Resource-based Instruction
Grouping",
// e.g. integer divides that only execute in the second slot.
//
-// Note: on the PPC970, logical CR operations are more expensive in their three
-// address form: ops that read/write the same register are half as expensive as
-//
void PPCHazardRecognizer970::EndDispatchGroup() {
DEBUG(std::cerr << "=== Start of dispatch group\n");
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