Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.92 -> 1.93
PPCISelLowering.h updated: 1.23 -> 1.24
README.txt updated: 1.65 -> 1.66
---
Log message:
Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.
---
Diffs of the changes: (+42 -25)
PPCISelLowering.cpp | 40 ++++++++++++++++++++++++++++++++++++++++
PPCISelLowering.h | 2 ++
README.txt | 25 -------------------------
3 files changed, 42 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.92
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.93
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.92 Tue Feb 28 19:11:20 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Feb 28 22:57:39 2006
@@ -185,6 +185,9 @@
setSetCCResultContents(ZeroOrOneSetCCResult);
setStackPointerRegisterToSaveRestore(PPC::R1);
+ // We have target-specific dag combine patterns for the following nodes:
+ setTargetDAGCombine(ISD::SINT_TO_FP);
+
computeRegisterProperties();
}
@@ -997,6 +1000,43 @@
return BB;
}
+SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ TargetMachine &TM = getTargetMachine();
+ SelectionDAG &DAG = DCI.DAG;
+ switch (N->getOpcode()) {
+ default: break;
+ case ISD::SINT_TO_FP:
+ if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
+ // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
+ // We allow the src/dst to be either f32/f64, but force the intermediate
+ // type to be i64.
+ if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT &&
+ N->getOperand(0).getValueType() == MVT::i64) {
+
+ SDOperand Val = N->getOperand(0).getOperand(0);
+ if (Val.getValueType() == MVT::f32) {
+ Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
+ DCI.AddToWorklist(Val.Val);
+ }
+
+ Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
+ DCI.AddToWorklist(Val.Val);
+ Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
+ DCI.AddToWorklist(Val.Val);
+ if (N->getValueType(0) == MVT::f32) {
+ Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
+ DCI.AddToWorklist(Val.Val);
+ }
+ return Val;
+ }
+ }
+ break;
+ }
+
+ return SDOperand();
+}
+
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
PPCTargetLowering::ConstraintType
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.23
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.24
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.23 Tue Feb 21 18:56:38 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Tue Feb 28 22:57:39 2006
@@ -81,6 +81,8 @@
///
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+
/// LowerArguments - This hook must be implemented to indicate how we
should
/// lower the arguments for the specified function, into the specified DAG.
virtual std::vector<SDOperand>
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.65
llvm/lib/Target/PowerPC/README.txt:1.66
--- llvm/lib/Target/PowerPC/README.txt:1.65 Tue Feb 28 00:36:04 2006
+++ llvm/lib/Target/PowerPC/README.txt Tue Feb 28 22:57:39 2006
@@ -328,31 +328,6 @@
Compile this:
-double %test(double %X) {
- %Y = cast double %X to long
- %Z = cast long %Y to double
- ret double %Z
-}
-
-to this:
-
-_test:
- fctidz f0, f1
- stfd f0, -8(r1)
- lwz r2, -4(r1)
- lwz r3, -8(r1)
- stw r2, -12(r1)
- stw r3, -16(r1)
- lfd f0, -16(r1)
- fcfid f1, f0
- blr
-
-without the lwz/stw's.
-
-===-------------------------------------------------------------------------===
-
-Compile this:
-
int foo(int a) {
int b = (a < 8);
if (b) {
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