Changes in directory llvm/lib/Target/PowerPC:
PPC.td updated: 1.11 -> 1.12
PPCSubtarget.h updated: 1.12 -> 1.13
---
Log message:
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
---
Diffs of the changes: (+6 -2)
PPC.td | 6 ++++--
PPCSubtarget.h | 2 ++
2 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC.td
diff -u llvm/lib/Target/PowerPC/PPC.td:1.11 llvm/lib/Target/PowerPC/PPC.td:1.12
--- llvm/lib/Target/PowerPC/PPC.td:1.11 Fri Jan 27 02:09:42 2006
+++ llvm/lib/Target/PowerPC/PPC.td Tue Feb 28 01:08:22 2006
@@ -29,6 +29,8 @@
"Enable GPUL instructions">;
def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
"Enable the fsqrt instruction">;
+def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
+ "Enable the stfiwx instruction">;
//===----------------------------------------------------------------------===//
// Register File Description
@@ -58,10 +60,10 @@
def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
def : Processor<"750", G3Itineraries, []>;
def : Processor<"970", G5Itineraries,
- [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+ [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Feature64Bit /*, Feature64BitRegs */]>;
def : Processor<"g5", G5Itineraries,
- [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+ [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Feature64Bit /*, Feature64BitRegs */]>;
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
diff -u llvm/lib/Target/PowerPC/PPCSubtarget.h:1.12
llvm/lib/Target/PowerPC/PPCSubtarget.h:1.13
--- llvm/lib/Target/PowerPC/PPCSubtarget.h:1.12 Tue Nov 1 14:07:00 2005
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h Tue Feb 28 01:08:22 2006
@@ -37,6 +37,7 @@
bool Has64BitRegs;
bool HasAltivec;
bool HasFSQRT;
+ bool HasSTFIWX;
bool IsAIX;
bool IsDarwin;
public:
@@ -60,6 +61,7 @@
bool hasFSQRT() const { return HasFSQRT; }
+ bool hasSTFIWX() const { return HasSTFIWX; }
bool has64BitRegs() const { return Has64BitRegs; }
bool hasAltivec() const { return HasAltivec; }
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