Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.44 -> 1.45
X86InstrInfo.td updated: 1.234 -> 1.235
X86RegisterInfo.cpp updated: 1.123 -> 1.124
---
Log message:
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
---
Diffs of the changes: (+29 -13)
X86InstrInfo.cpp | 1 +
X86InstrInfo.td | 31 ++++++++++++++++++++-----------
X86RegisterInfo.cpp | 10 ++++++++--
3 files changed, 29 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.44
llvm/lib/Target/X86/X86InstrInfo.cpp:1.45
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.44 Thu Feb 2 14:38:12 2006
+++ llvm/lib/Target/X86/X86InstrInfo.cpp Thu Feb 16 16:45:16 2006
@@ -29,6 +29,7 @@
MachineOpCode oc = MI.getOpcode();
if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
+ oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
oc == X86::MOVAPSrr || oc == X86::MOVAPDrr) {
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.234
llvm/lib/Target/X86/X86InstrInfo.td:1.235
--- llvm/lib/Target/X86/X86InstrInfo.td:1.234 Thu Feb 16 13:34:41 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Thu Feb 16 16:45:17 2006
@@ -2487,13 +2487,13 @@
[(X86cmp FR64:$src1, (loadf64 addr:$src2))]>,
Requires<[HasSSE2]>, TB, OpSize;
-// Pseudo-instructions that map fld0 to xorps/xorpd for sse.
+// Pseudo-instructions that map fld0 to pxor for sse.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-def FLD0SS : I<0x57, MRMInitReg, (ops FR32:$dst),
- "xorps $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
+def FLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
+ "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
Requires<[HasSSE1]>, TB;
-def FLD0SD : I<0x57, MRMInitReg, (ops FR64:$dst),
- "xorpd $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
+def FLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
+ "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
Requires<[HasSSE2]>, TB, OpSize;
let isTwoAddress = 1 in {
@@ -3033,13 +3033,22 @@
"movapd {$src, $dst|$dst, $src}",[]>,
Requires<[HasSSE2]>, TB, OpSize;
-// Pseudo-instructions to load FR32 / FR64 from f128mem using movaps / movapd.
+// Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
// Upper bits are disregarded.
-def MOVSAPSrm : I<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
- "movaps {$src, $dst|$dst, $src}",
- [(set FR32:$dst, (X86loadpf32 addr:$src))]>,
- Requires<[HasSSE1]>, TB;
-def MOVSAPDrm : I<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
+def FsMOVAPSrr : I<0x28, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
+ "movaps {$src, $dst|$dst, $src}", []>,
+ Requires<[HasSSE1]>, TB;
+def FsMOVAPDrr : I<0x28, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
+ "movapd {$src, $dst|$dst, $src}", []>,
+ Requires<[HasSSE2]>, TB, OpSize;
+
+// Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
+// Upper bits are disregarded.
+def FsMOVAPSrm : I<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
+ "movaps {$src, $dst|$dst, $src}",
+ [(set FR32:$dst, (X86loadpf32 addr:$src))]>,
+ Requires<[HasSSE1]>, TB;
+def FsMOVAPDrm : I<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
"movapd {$src, $dst|$dst, $src}",
[(set FR64:$dst, (X86loadpf64 addr:$src))]>,
Requires<[HasSSE2]>, TB, OpSize;
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.123
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.124
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.123 Thu Feb 16 15:20:26 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 16 16:45:17 2006
@@ -114,9 +114,9 @@
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpMOV;
} else if (RC == &X86::FR32RegClass || RC == &X86::V4F4RegClass) {
- Opc = X86::MOVAPSrr;
+ Opc = X86::FsMOVAPSrr;
} else if (RC == &X86::FR64RegClass || RC == &X86::V2F8RegClass) {
- Opc = X86::MOVAPDrr;
+ Opc = X86::FsMOVAPDrr;
} else {
assert(0 && "Unknown regclass");
abort();
@@ -313,6 +313,9 @@
case X86::CMP8ri: return MakeMIInst(X86::CMP8mi , FrameIndex, MI);
case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
+ // Alias scalar SSE instructions
+ case X86::FsMOVAPSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
+ case X86::FsMOVAPDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
// Scalar SSE instructions
case X86::MOVSSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
case X86::MOVSDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
@@ -393,6 +396,9 @@
case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI);
case X86::MOVZX32rr8:return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI);
case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI);
+ // Alias scalar SSE instructions
+ case X86::FsMOVAPSrr:return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
+ case X86::FsMOVAPDrr:return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);
// Scalar SSE instructions
case X86::MOVSSrr: return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
case X86::MOVSDrr: return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);
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