Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.83 -> 1.84
README.txt updated: 1.51 -> 1.52
---
Log message:
Fix some of the stuff in the PPC README file, and clean up legalization
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
---
Diffs of the changes: (+38 -53)
PPCISelLowering.cpp | 49 ++++++++++++++++++++++++++++++++++++++-----------
README.txt | 42 ------------------------------------------
2 files changed, 38 insertions(+), 53 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.83
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.84
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.83 Tue Jan 31 16:21:34 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Feb 1 01:19:44 2006
@@ -13,6 +13,7 @@
#include "PPCISelLowering.h"
#include "PPCTargetMachine.h"
+#include "llvm/ADT/VectorExtras.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -20,7 +21,7 @@
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
-#include "llvm/ADT/VectorExtras.h"
+#include "llvm/Support/MathExtras.h"
using namespace llvm;
PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
@@ -85,7 +86,7 @@
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
- // PowerPC wants to optimize setcc i32, imm a bit.
+ // PowerPC wants to optimize integer setcc a bit
setOperationAction(ISD::SETCC, MVT::i32, Custom);
// PowerPC does not have BRCOND* which requires SetCC
@@ -452,15 +453,41 @@
}
case ISD::SETCC: {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
- if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
- if (C->getValue() && !C->isAllOnesValue())
- if (CC == ISD::SETEQ || CC == ISD::SETNE ||
- CC == ISD::SETLT || CC == ISD::SETGT) {
- MVT::ValueType VT = Op.getValueType();
- SDOperand SUB = DAG.getNode(ISD::SUB,
Op.getOperand(0).getValueType(),
- Op.getOperand(0), Op.getOperand(1));
- return DAG.getSetCC(VT, SUB, DAG.getConstant(0, VT), CC);
- }
+
+ // If we're comparing for equality to zero, expose the fact that this is
+ // implented as a ctlz/srl pair on ppc, so that the dag combiner can
+ // fold the new nodes.
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+ if (C->isNullValue() && CC == ISD::SETEQ) {
+ MVT::ValueType VT = Op.getOperand(0).getValueType();
+ SDOperand Zext = Op.getOperand(0);
+ if (VT < MVT::i32) {
+ VT = MVT::i32;
+ Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
+ }
+ unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
+ SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
+ SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
+ DAG.getConstant(Log2b,
getShiftAmountTy()));
+ return DAG.getNode(ISD::TRUNCATE, getSetCCResultTy(), Scc);
+ }
+ // Leave comparisons against 0 and -1 alone for now, since they're
usually
+ // optimized. FIXME: revisit this when we can custom lower all setcc
+ // optimizations.
+ if (C->isAllOnesValue() || C->isNullValue())
+ break;
+ }
+
+ // If we have an integer seteq/setne, turn it into a compare against zero
+ // by subtracting the rhs from the lhs, which is faster than setting a
+ // condition register, reading it back out, and masking the correct bit.
+ MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
+ if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
+ MVT::ValueType VT = Op.getValueType();
+ SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
+ Op.getOperand(1));
+ return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
+ }
break;
}
case ISD::VASTART: {
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.51
llvm/lib/Target/PowerPC/README.txt:1.52
--- llvm/lib/Target/PowerPC/README.txt:1.51 Tue Jan 31 18:28:12 2006
+++ llvm/lib/Target/PowerPC/README.txt Wed Feb 1 01:19:44 2006
@@ -280,32 +280,6 @@
===-------------------------------------------------------------------------===
-For this:
-
-int h(int i, int j, int k) {
- return (i==0||j==0||k == 0);
-}
-
-We currently emit this:
-
-_h:
- cntlzw r2, r3
- cntlzw r3, r4
- cntlzw r4, r5
- srwi r2, r2, 5
- srwi r3, r3, 5
- srwi r4, r4, 5
- or r2, r3, r2
- or r3, r2, r4
- blr
-
-The ctlz/shift instructions are created by the isel, so the dag combiner
doesn't
-have a chance to pull the shifts through the or's (eliminating two
-instructions). SETCC nodes should be custom lowered in this case, not expanded
-by the isel.
-
-===-------------------------------------------------------------------------===
-
Darwin Stub LICM optimization:
Loops like this:
@@ -461,19 +435,3 @@
same operands (but backwards) exists. In this case, this wouldn't save us
anything though, because the compares still wouldn't be shared.
-===-------------------------------------------------------------------------===
-
-A simple case we generate suboptimal code on:
-
-int test(int X) {
- return X == 0 ? 32 : 0;
-}
-
-_test:
- cntlzw r2, r3
- srwi r2, r2, 5
- slwi r3, r2, 5
- blr
-
-The shifts should be one 'andi'.
-
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