[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.80 -> 1.81
---
Log message:

Codegen 

bool %test(int %X) {
  %Y = seteq int %X, 13
  ret bool %Y
}

as

_test:
        addi r2, r3, -13
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

rather than

_test:
        cmpwi cr7, r3, 13
        mfcr r2
        rlwinm r3, r2, 31, 31, 31
        blr

This has very little effect on most code, but speeds up analyzer 23% and
mason 11%


---
Diffs of the changes:  (+16 -0)

 PPCISelLowering.cpp |   16 ++++++++++++++++
 1 files changed, 16 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.80 
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.81
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.80    Sun Jan 29 14:49:17 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jan 31 02:17:29 2006
@@ -83,6 +83,9 @@
   // PowerPC wants to turn select_cc of FP into fsel when possible.
   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
+
+  // PowerPC wants to optimize setcc i32, imm a bit.
+  setOperationAction(ISD::SETCC, MVT::i32, Custom);
   
   // PowerPC does not have BRCOND* which requires SetCC
   setOperationAction(ISD::BRCOND,       MVT::Other, Expand);
@@ -445,6 +448,19 @@
     // resolution stub.
     return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
   }
+  case ISD::SETCC: {
+    ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
+    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
+      if (C->getValue() && !C->isAllOnesValue())
+        if (CC == ISD::SETEQ || CC == ISD::SETNE || 
+            CC == ISD::SETLT || CC == ISD::SETGT) {
+          MVT::ValueType VT = Op.getValueType();
+          SDOperand SUB = DAG.getNode(ISD::SUB, 
Op.getOperand(0).getValueType(),
+                                      Op.getOperand(0), Op.getOperand(1));
+          return DAG.getSetCC(VT, SUB, DAG.getConstant(0, VT), CC);
+        }
+    break;
+  }
   case ISD::VASTART: {
     // vastart just stores the address of the VarArgsFrameIndex slot into the
     // memory location argument.



_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits