Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.20 -> 1.21
AlphaISelLowering.cpp updated: 1.14 -> 1.15
AlphaISelLowering.h updated: 1.6 -> 1.7
AlphaISelPattern.cpp updated: 1.195 -> 1.196
AlphaInstrInfo.td updated: 1.87 -> 1.88
---
Log message:
All addressing modes are now exposed. The only remaining relocated forms
are for function prologue.
TODO: move external symbols over to using RelLit.
: have a pattern that matches constpool|globaladdr
: have a pattern that matches (add x imm) -> x, imm or (...) -> ..., 0
---
Diffs of the changes: (+48 -27)
AlphaISelDAGToDAG.cpp | 6 ------
AlphaISelLowering.cpp | 2 +-
AlphaISelLowering.h | 11 +++++------
AlphaISelPattern.cpp | 17 +++++------------
AlphaInstrInfo.td | 39 +++++++++++++++++++++++++++++++++++++--
5 files changed, 48 insertions(+), 27 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.20
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.21
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.20 Fri Dec 23 23:36:33 2005
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Sat Dec 24 02:29:32 2005
@@ -212,12 +212,6 @@
Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
getGlobalBaseReg());
return CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
}
- case ISD::TargetGlobalAddress: {
- GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
- SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
- return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA,
- getGlobalBaseReg());
- }
case ISD::ExternalSymbol:
return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64,
CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
MVT::i64),
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.14
llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.15
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.14 Fri Dec 23 23:36:33 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Sat Dec 24 02:29:32 2005
@@ -459,7 +459,7 @@
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
return Lo;
} else
- return GA;
+ return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
}
}
Index: llvm/lib/Target/Alpha/AlphaISelLowering.h
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.6
llvm/lib/Target/Alpha/AlphaISelLowering.h:1.7
--- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.6 Fri Dec 23 23:36:33 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.h Sat Dec 24 02:29:32 2005
@@ -29,12 +29,11 @@
ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_,
/// GPRelHi/GPRelLo - These represent the high and low 16-bit
- /// parts of a global address respectively. These nodes have
- /// two operands, the first of which must be a
- /// TargetGlobalAddress, and the second of which must be a
- /// Constant. Selected naively, these turn into 'ldah R(G)' and
- /// 'lda R(C)', though these are usually folded into other nodes.
- GPRelHi, GPRelLo,
+ /// parts of a global address respectively.
+ GPRelHi, GPRelLo,
+
+ /// RetLit - Literal Relocation of a Global
+ RelLit,
/// GlobalBaseReg, used to restore the GOT ptr
GlobalBaseReg,
Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.195
llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.196
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.195 Fri Dec 23 23:36:33 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Sat Dec 24 02:29:32 2005
@@ -744,20 +744,13 @@
else assert(0 && "unknown Lo part");
return Result;
- case ISD::GlobalAddress:
- AlphaLowering.restoreGP(BB);
- has_sym = true;
-
- Reg = Result = MakeReg(MVT::i64);
-
- if (EnableAlphaLSMark)
- BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
- .addImm(getUID());
-
+ case AlphaISD::RelLit: {
+ GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N.getOperand(0));
BuildMI(BB, Alpha::LDQl, 2, Result)
- .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal())
- .addReg(Alpha::R29);
+ .addGlobalAddress(GASD->getGlobal())
+ .addReg(SelectExpr(N.getOperand(1)));
return Result;
+ }
case ISD::ExternalSymbol:
AlphaLowering.restoreGP(BB);
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.87
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.88
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.87 Sat Dec 24 01:34:33 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Sat Dec 24 02:29:32 2005
@@ -27,6 +27,7 @@
def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_", SDTFPUnaryOp, []>;
def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
+def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>;
// These are target-independent nodes, but have target-specific formats.
def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
@@ -505,6 +506,26 @@
[(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP,
GPRC:$RB)))]>;
}
+
+//constpool rels
+def : Pat<(i64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
+ (LDQr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (sextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i32)),
+ (LDLr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i8)),
+ (LDBUr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i16)),
+ (LDWUr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (Alpha_gprello tconstpool:$DISP, GPRC:$RB)),
+ (LDAr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (Alpha_gprelhi tconstpool:$DISP, GPRC:$RB)),
+ (LDAHr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(f32 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
+ (LDSr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(f64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
+ (LDTr tconstpool:$DISP, GPRC:$RB)>;
+
+
//misc ext patterns
def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i8)),
(LDBU immSExt16:$DISP, GPRC:$RB)>;
@@ -533,6 +554,19 @@
def : Pat<(i64 (extload GPRC:$addr, i32)),
(LDL 0, GPRC:$addr)>;
+def : Pat<(store GPRC:$DATA, GPRC:$addr),
+ (STQ GPRC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(store F8RC:$DATA, GPRC:$addr),
+ (STT F8RC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(store F4RC:$DATA, GPRC:$addr),
+ (STS F4RC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i32),
+ (STL GPRC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i16),
+ (STW GPRC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i8),
+ (STB GPRC:$DATA, 0, GPRC:$addr)>;
+
//load address, rellocated gpdist form
let OperandList = (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
@@ -541,8 +575,9 @@
}
//Load quad, rellocated literal form
-let isLoad = 1, OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in
-def LDQl : MFormAlt<0x29, "ldq $RA,$DISP($RB)\t\t!literal">; //Load quadword
+let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in
+def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
+ [(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))]>;
//Branches, int
def BEQ : BForm<0x39, "beq $RA,$DISP">; //Branch if = zero
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