Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.18 -> 1.19
AlphaInstrFormats.td updated: 1.18 -> 1.19
AlphaInstrInfo.td updated: 1.84 -> 1.85
---
Log message:
move loads and stores over. Smart addr selection comming
---
Diffs of the changes: (+53 -58)
AlphaISelDAGToDAG.cpp | 58 --------------------------------------------------
AlphaInstrFormats.td | 12 ++++++++++
AlphaInstrInfo.td | 41 +++++++++++++++++++++++++++++++++++
3 files changed, 53 insertions(+), 58 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.18
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.19
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.18 Mon Dec 12 14:30:09 2005
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Fri Dec 23 21:41:56 2005
@@ -35,7 +35,6 @@
//===--------------------------------------------------------------------===//
/// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
/// instructions for SelectionDAG operations.
- ///
class AlphaDAGToDAGISel : public SelectionDAGISel {
AlphaTargetLowering AlphaLowering;
@@ -194,63 +193,6 @@
return CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC,
CurDAG->getBasicBlock(Dest), Chain);
}
- case ISD::LOAD:
- case ISD::EXTLOAD:
- case ISD::ZEXTLOAD:
- case ISD::SEXTLOAD: {
- SDOperand Chain = Select(N->getOperand(0));
- SDOperand Address = Select(N->getOperand(1));
- unsigned opcode = N->getOpcode();
- unsigned Opc = Alpha::WTF;
- if (opcode == ISD::LOAD)
- switch (N->getValueType(0)) {
- default: N->dump(); assert(0 && "Bad load!");
- case MVT::i64: Opc = Alpha::LDQ; break;
- case MVT::f64: Opc = Alpha::LDT; break;
- case MVT::f32: Opc = Alpha::LDS; break;
- }
- else
- switch (cast<VTSDNode>(N->getOperand(3))->getVT()) {
- default: N->dump(); assert(0 && "Bad sign extend!");
- case MVT::i32: Opc = Alpha::LDL;
- assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
- case MVT::i16: Opc = Alpha::LDWU;
- assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
- case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
- case MVT::i8: Opc = Alpha::LDBU;
- assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
- }
-
- return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
- getI64Imm(0), Address,
- Chain).getValue(Op.ResNo);
- }
- case ISD::STORE:
- case ISD::TRUNCSTORE: {
- SDOperand Chain = Select(N->getOperand(0));
- SDOperand Value = Select(N->getOperand(1));
- SDOperand Address = Select(N->getOperand(2));
-
- unsigned Opc = Alpha::WTF;
-
- if (N->getOpcode() == ISD::STORE) {
- switch (N->getOperand(1).getValueType()) {
- case MVT::i64: Opc = Alpha::STQ; break;
- case MVT::f64: Opc = Alpha::STT; break;
- case MVT::f32: Opc = Alpha::STS; break;
- default: assert(0 && "Bad store!");
- };
- } else { //TRUNCSTORE
- switch (cast<VTSDNode>(N->getOperand(4))->getVT()) {
- case MVT::i32: Opc = Alpha::STL; break;
- case MVT::i16: Opc = Alpha::STW; break;
- case MVT::i8: Opc = Alpha::STB; break;
- default: assert(0 && "Bad truncstore!");
- };
- }
- return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Value, getI64Imm(0),
- Address, Chain);
- }
case ISD::BR:
return CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1),
Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td
diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.18
llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.19
--- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.18 Tue Dec 6 14:40:34 2005
+++ llvm/lib/Target/Alpha/AlphaInstrFormats.td Fri Dec 23 21:41:56 2005
@@ -40,6 +40,18 @@
}
//3.3.1
+class MFormD<bits<6> opcode, string asmstr, list<dag> pattern>
+ : InstAlphaAlt<opcode, asmstr> {
+ let Pattern = pattern;
+
+ bits<5> Ra;
+ bits<16> disp;
+ bits<5> Rb;
+
+ let Inst{25-21} = Ra;
+ let Inst{20-16} = Rb;
+ let Inst{15-0} = disp;
+}
class MFormAlt<bits<6> opcode, string asmstr>
: InstAlphaAlt<opcode, asmstr> {
bits<5> Ra;
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.84
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.85
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.84 Mon Dec 12 14:30:09 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Fri Dec 23 21:41:56 2005
@@ -436,6 +436,47 @@
def BR_DAG : BFormD<0x30, "br $$31,$DISP">; //Branch
+
+let isLoad = 1, OperandList = (ops GPRC:$RA, GPRC:$RB), disp = 0 in {
+def LDQdag : MFormD<0x29, "ldq $RA,0($RB)",
+ [(set GPRC:$RA, (load GPRC:$RB))]>;
+def LDLdag : MFormD<0x29, "ldl $RA,0($RB)",
+ [(set GPRC:$RA, (sextload GPRC:$RB, i32))]>;
+def LDBUdag : MFormD<0x0A, "ldbu $RA,0($RB)",
+ [(set GPRC:$RA, (zextload GPRC:$RB, i8))]>;
+def LDWUdag : MFormD<0x0C, "ldwu $RA,0($RB)",
+ [(set GPRC:$RA, (zextload GPRC:$RB, i16))]>;
+
+def STBdag : MFormD<0x0E, "stb $RA,0($RB)",
+ [(truncstore GPRC:$RA, GPRC:$RB, i8)]>;
+def STWdag : MFormD<0x0D, "stw $RA,0($RB)",
+ [(truncstore GPRC:$RA, GPRC:$RB, i16)]>;
+def STLdag : MFormD<0x2C, "stl $RA,0($RB)",
+ [(truncstore GPRC:$RA, GPRC:$RB, i32)]>;
+def STQdag : MFormD<0x2D, "stq $RA,0($RB)",
+ [(store GPRC:$RA, GPRC:$RB)]>;
+}
+
+def : Pat<(i64 (extload GPRC:$src, i8)),
+ (LDBUdag GPRC:$src)>;
+def : Pat<(i64 (extload GPRC:$src, i16)),
+ (LDWUdag GPRC:$src)>;
+def : Pat<(i64 (extload GPRC:$src, i32)),
+ (LDLdag GPRC:$src)>;
+
+let isLoad = 1, OperandList = (ops F4RC:$RA, GPRC:$RB), disp = 0 in {
+def STSdag : MFormD<0x26, "sts $RA,0($RB)",
+ [(store F4RC:$RA, GPRC:$RB)]>;
+def LDSdag : MFormD<0x22, "lds $RA,0($RB)",
+ [(set F4RC:$RA, (load GPRC:$RB))]>;
+}
+let isLoad = 1, OperandList = (ops F8RC:$RA, GPRC:$RB), disp = 0 in {
+def STTdag : MFormD<0x27, "stt $RA,0($RB)",
+ [(store F8RC:$RA, GPRC:$RB)]>;
+def LDTdag : MFormD<0x23, "ldt $RA,0($RB)",
+ [(set F8RC:$RA, (load GPRC:$RB))]>;
+}
+
//Stores, int
def STB : MForm<0x0E, "stb $RA,$DISP($RB)">; // Store byte
def STW : MForm<0x0D, "stw $RA,$DISP($RB)">; // Store word
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