Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.25 -> 1.26
---
Log message:
* Promote all 1 bit entities to 8 bit.
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
---
Diffs of the changes: (+4 -1)
TargetSelectionDAG.td | 5 ++++-
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.25
llvm/lib/Target/TargetSelectionDAG.td:1.26
--- llvm/lib/Target/TargetSelectionDAG.td:1.25 Thu Dec 15 02:29:48 2005
+++ llvm/lib/Target/TargetSelectionDAG.td Thu Dec 15 13:49:22 2005
@@ -150,7 +150,7 @@
SDTCisPtrTy<1>
]>;
-def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload
+def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload, extload
SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
]>;
@@ -261,6 +261,7 @@
// below) which pass in a dummy srcvalue node which tblgen will skip over.
def sextld : SDNode<"ISD::SEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>;
def zextld : SDNode<"ISD::ZEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>;
+def extld : SDNode<"ISD::EXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>;
//===----------------------------------------------------------------------===//
// Selection DAG Condition Codes
@@ -333,6 +334,8 @@
(sextld node:$ptr, srcvalue:$dummy, node:$vt)>;
def zextload : PatFrag<(ops node:$ptr, node:$vt),
(zextld node:$ptr, srcvalue:$dummy, node:$vt)>;
+def extload : PatFrag<(ops node:$ptr, node:$vt),
+ (extld node:$ptr, srcvalue:$dummy, node:$vt)>;
// setcc convenience fragments.
def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
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