Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.11 -> 1.12
X86ISelLowering.cpp updated: 1.6 -> 1.7
X86InstrInfo.td updated: 1.168 -> 1.169
---
Log message:
* Promote all 1 bit entities to 8 bit.
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
---
Diffs of the changes: (+5 -113)
X86ISelDAGToDAG.cpp | 107 ----------------------------------------------------
X86ISelLowering.cpp | 3 -
X86InstrInfo.td | 8 ++-
3 files changed, 5 insertions(+), 113 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.11
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.12
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.11 Wed Dec 14 19:02:48 2005
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Dec 15 13:49:23 2005
@@ -22,7 +22,6 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
#include "llvm/ADT/Statistic.h"
-#include <set>
using namespace llvm;
//===----------------------------------------------------------------------===//
@@ -96,8 +95,6 @@
private:
SDOperand Select(SDOperand N);
- bool isFoldableLoad(SDOperand Op, SDOperand OtherOp,
- bool FloatPromoteOk = false);
bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp);
@@ -362,68 +359,6 @@
return false;
}
-/// NodeTransitivelyUsesValue - Return true if N or any of its uses uses Op.
-/// The DAG cannot have cycles in it, by definition, so the visited set is not
-/// needed to prevent infinite loops. The DAG CAN, however, have unbounded
-/// reuse, so it prevents exponential cases.
-///
-static bool NodeTransitivelyUsesValue(SDOperand N, SDOperand Op,
- std::set<SDNode*> &Visited) {
- if (N == Op) return true; // Found it.
- SDNode *Node = N.Val;
- if (Node->getNumOperands() == 0 || // Leaf?
- Node->getNodeDepth() <= Op.getNodeDepth()) return false; // Can't find
it?
- if (!Visited.insert(Node).second) return false; // Already visited?
-
- // Recurse for the first N-1 operands.
- for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
- if (NodeTransitivelyUsesValue(Node->getOperand(i), Op, Visited))
- return true;
-
- // Tail recurse for the last operand.
- return NodeTransitivelyUsesValue(Node->getOperand(0), Op, Visited);
-}
-
-/// isFoldableLoad - Return true if this is a load instruction that can safely
-/// be folded into an operation that uses it.
-bool X86DAGToDAGISel::isFoldableLoad(SDOperand Op, SDOperand OtherOp,
- bool FloatPromoteOk) {
- if (Op.getOpcode() == ISD::LOAD) {
- // FIXME: currently can't fold constant pool indexes.
- if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
- return false;
- } else if (FloatPromoteOk && Op.getOpcode() == ISD::EXTLOAD &&
- cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::f32) {
- // FIXME: currently can't fold constant pool indexes.
- if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
- return false;
- } else {
- return false;
- }
-
- // If this load has already been emitted, we clearly can't fold it.
- assert(Op.ResNo == 0 && "Not a use of the value of the load?");
- if (CodeGenMap.count(Op.getValue(1))) return false;
- assert(!CodeGenMap.count(Op.getValue(0)) &&
- "Value in map but not token chain?");
- assert(!CodeGenMap.count(Op.getValue(1)) &&
- "Token lowered but value not in map?");
-
- // If there is not just one use of its value, we cannot fold.
- if (!Op.Val->hasNUsesOfValue(1, 0)) return false;
-
- // Finally, we cannot fold the load into the operation if this would induce a
- // cycle into the resultant dag. To check for this, see if OtherOp (the
other
- // operand of the operation we are folding the load into) can possible use
the
- // chain node defined by the load.
- if (OtherOp.Val && !Op.Val->hasNUsesOfValue(0, 1)) { // Has uses of chain?
- std::set<SDNode*> Visited;
- if (NodeTransitivelyUsesValue(OtherOp, Op.getValue(1), Visited))
- return false;
- }
- return true;
-}
-
SDOperand X86DAGToDAGISel::Select(SDOperand N) {
SDNode *Node = N.Val;
MVT::ValueType NVT = Node->getValueType(0);
@@ -455,48 +390,6 @@
}
break;
- case ISD::ANY_EXTEND: // treat any extend like zext
- case ISD::ZERO_EXTEND: {
- SDOperand N0 = N.getOperand(0);
- if (N0.getValueType() == MVT::i1) {
- // FIXME: This hack is here for zero extension casts from bool to i8.
- // This would not be needed if bools were promoted by Legalize.
- if (NVT == MVT::i8) {
- Opc = X86::MOV8rr;
- } else if (!isFoldableLoad(N0, SDOperand())) {
- switch (NVT) {
- default: assert(0 && "Cannot zero extend to this type!");
- case MVT::i16: Opc = X86::MOVZX16rr8; break;
- case MVT::i32: Opc = X86::MOVZX32rr8; break;
- }
- } else {
- switch (NVT) {
- default: assert(0 && "Cannot zero extend to this type!");
- case MVT::i16: Opc = X86::MOVZX16rm8; break;
- case MVT::i32: Opc = X86::MOVZX32rm8; break;
- }
-
- SDOperand Chain = Select(N0.getOperand(0));
- SDOperand Base, Scale, Index, Disp;
- (void) SelectAddr(N0.getOperand(1), Base, Scale, Index, Disp);
- SDOperand Result = CurDAG->getTargetNode(Opc, NVT,
- MVT::Other, Base, Scale,
- Index, Disp, Chain);
- CodeGenMap[N.getValue(0)] = Result;
- Chain = CodeGenMap[N.getValue(1)] = Result.getValue(1);
- return (N.ResNo) ? Chain : Result.getValue(0);
- }
-
- SDOperand Tmp0 = Select(Node->getOperand(0));
- if (Node->hasOneUse())
- return CurDAG->SelectNodeTo(Node, Opc, NVT, Tmp0);
- else
- return CodeGenMap[N] = CurDAG->getTargetNode(Opc, NVT, Tmp0);
- }
- // Other cases are autogenerated.
- break;
- }
-
case ISD::RET: {
SDOperand Chain = Node->getOperand(0); // Token chain.
unsigned NumOps = Node->getNumOperands();
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.6
llvm/lib/Target/X86/X86ISelLowering.cpp:1.7
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.6 Wed Dec 7 11:59:14 2005
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Dec 15 13:49:23 2005
@@ -41,9 +41,6 @@
setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
// Set up the register classes.
- // FIXME: Eliminate these two classes when legalize can handle promotions
- // well.
- addRegisterClass(MVT::i1, X86::R8RegisterClass);
addRegisterClass(MVT::i8, X86::R8RegisterClass);
addRegisterClass(MVT::i16, X86::R16RegisterClass);
addRegisterClass(MVT::i32, X86::R32RegisterClass);
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.168
llvm/lib/Target/X86/X86InstrInfo.td:1.169
--- llvm/lib/Target/X86/X86InstrInfo.td:1.168 Thu Dec 15 02:31:04 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Thu Dec 15 13:49:23 2005
@@ -180,6 +180,8 @@
def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>;
def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>;
+def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>;
+
//===----------------------------------------------------------------------===//
// Instruction templates...
@@ -432,9 +434,6 @@
"mov{l} {$src, $dst|$dst, $src}",
[(store R32:$src, addr:$dst)]>;
-// Handling 1 bit load
-def : Pat<(i1 (load addr:$src)), (MOV8rm addr:$src)>;
-
//===----------------------------------------------------------------------===//
// Fixed-Register Multiplication and Division Instructions...
//
@@ -1720,6 +1719,9 @@
def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
+// Handling 1 bit extload
+def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
+
//===----------------------------------------------------------------------===//
// XMM Floating point support (requires SSE2)
//===----------------------------------------------------------------------===//
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