Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.h updated: 1.11 -> 1.12
PPCInstrInfo.td updated: 1.155 -> 1.156
---
Log message:
Prepare support for AltiVec multiply, divide, and sqrt.
---
Diffs of the changes: (+16 -2)
PPCISelLowering.h | 4 ++++
PPCInstrInfo.td | 14 ++++++++++++--
2 files changed, 16 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.11
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.12
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.11 Mon Dec 5 20:10:38 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Tue Dec 13 16:55:21 2005
@@ -39,6 +39,10 @@
/// of that FP value.
FCTIDZ, FCTIWZ,
+ // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
+ // three v4f32 operands and producing a v4f32 result.
+ VMADDFP, VNMSUBFP,
+
/// Hi/Lo - These represent the high and low 16-bit parts of a global
/// address respectively. These nodes have two operands, the first of
/// which must be a TargetGlobalAddress, and the second of which must be
a
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.155
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.156
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.155 Sun Dec 11 01:45:47 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Dec 13 16:55:22 2005
@@ -27,8 +27,10 @@
SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
-def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
-def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
+def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
+def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
+def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
+def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
// amounts. These nodes are generated by the multi-precision shift code.
@@ -949,6 +951,14 @@
def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
(ADDIS GPRC:$in, tconstpool:$g)>;
+// Fused multiply add and multiply sub for packed float. These are represented
+// separately from the real instructions above, for operations that must have
+// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
+def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
+ (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
+def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
+ (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
+
// Standard shifts. These are represented separately from the real shifts
above
// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
// amounts.
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