[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86InstrInfo.td updated: 1.152 -> 1.153
---
Log message:

Add a few more add / store patterns. e.g. ADD32mi8.


---
Diffs of the changes:  (+18 -10)

 X86InstrInfo.td |   28 ++++++++++++++++++----------
 1 files changed, 18 insertions(+), 10 deletions(-)


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.152 
llvm/lib/Target/X86/X86InstrInfo.td:1.153
--- llvm/lib/Target/X86/X86InstrInfo.td:1.152   Fri Dec  9 18:48:20 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Dec 12 13:45:23 2005
@@ -1206,21 +1206,29 @@
 
 let isTwoAddress = 0 in {
   def ADD8mr   : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
-                   "add{b} {$src2, $dst|$dst, $src2}", []>;
+                   "add{b} {$src2, $dst|$dst, $src2}",
+                   [(store (add (load addr:$dst), R8:$src2), addr:$dst)]>;
   def ADD16mr  : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2),
-                   "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
+                   "add{w} {$src2, $dst|$dst, $src2}",
+                   [(store (add (load addr:$dst), R16:$src2), addr:$dst)]>, 
OpSize;
   def ADD32mr  : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2),
-                   "add{l} {$src2, $dst|$dst, $src2}", []>;
+                   "add{l} {$src2, $dst|$dst, $src2}",
+                   [(store (add (load addr:$dst), R32:$src2), addr:$dst)]>;
   def ADD8mi   : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
-                     "add{b} {$src2, $dst|$dst, $src2}", []>;
+                     "add{b} {$src2, $dst|$dst, $src2}",
+                   [(store (add (load addr:$dst), (i8 imm:$src2)), 
addr:$dst)]>;
   def ADD16mi  : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
-                      "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
+                      "add{w} {$src2, $dst|$dst, $src2}",
+                   [(store (add (load addr:$dst), (i16 imm:$src2)), 
addr:$dst)]>, OpSize;
   def ADD32mi  : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
-                      "add{l} {$src2, $dst|$dst, $src2}", []>;
-  def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i8imm :$src2),
-                     "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
-  def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i8imm :$src2),
-                     "add{l} {$src2, $dst|$dst, $src2}", []>;
+                      "add{l} {$src2, $dst|$dst, $src2}",
+                   [(store (add (load addr:$dst), (i32 imm:$src2)), 
addr:$dst)]>;
+  def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2),
+                     "add{w} {$src2, $dst|$dst, $src2}",
+                   [(store (add (load addr:$dst), (i16 immSExt8:$src2)), 
addr:$dst)]>, OpSize;
+  def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2),
+                     "add{l} {$src2, $dst|$dst, $src2}",
+                   [(store (add (load addr:$dst), (i32 immSExt8:$src2)), 
addr:$dst)]>;
 }
 
 let isCommutable = 1 in {  // X = ADC Y, Z --> X = ADC Z, Y



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