Changes in directory llvm/lib/Target/Alpha:
AlphaRegisterInfo.td updated: 1.14 -> 1.15
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+3 -3)
AlphaRegisterInfo.td | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.td
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.14
llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.15
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.14 Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.td Wed Nov 30 22:51:06 2005
@@ -78,7 +78,7 @@
// $28 is undefined after any and all calls
/// Register classes
-def GPRC : RegisterClass<"Alpha", i64, 64,
+def GPRC : RegisterClass<"Alpha", [i64], 64,
// Volatile
[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
R23, R24, R25, R28,
@@ -102,7 +102,7 @@
}];
}
-def F4RC : RegisterClass<"Alpha", f32, 64, [F0, F1,
+def F4RC : RegisterClass<"Alpha", [f32], 64, [F0, F1,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
// Saved:
@@ -120,7 +120,7 @@
}];
}
-def F8RC : RegisterClass<"Alpha", f64, 64, [F0, F1,
+def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
// Saved:
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