Changes in directory llvm/lib/Target/IA64:
IA64RegisterInfo.td updated: 1.10 -> 1.11
---
Log message:
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
---
Diffs of the changes: (+3 -3)
IA64RegisterInfo.td | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.10
llvm/lib/Target/IA64/IA64RegisterInfo.td:1.11
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.10 Wed Nov 2 01:30:39 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.td Wed Nov 30 22:51:06 2005
@@ -232,7 +232,7 @@
// FIXME/XXX we also reserve r22 for calculating addresses
// in IA64RegisterInfo.cpp
-def GR : RegisterClass<"IA64", i64, 64,
+def GR : RegisterClass<"IA64", [i64], 64,
[
//FIXME!: for readability, we don't want the out registers to be the first
@@ -282,7 +282,7 @@
// these are the scratch (+stacked) FP registers
-def FP : RegisterClass<"IA64", f64, 64,
+def FP : RegisterClass<"IA64", [f64], 64,
[F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15,
F32, F33, F34, F35, F36, F37, F38, F39,
@@ -317,7 +317,7 @@
}
// these are the predicate registers, p0 (1/TRUE) is not here
-def PR : RegisterClass<"IA64", i1, 64,
+def PR : RegisterClass<"IA64", [i1], 64,
// for now, let's be wimps and only have the scratch predicate regs
[p6, p7, p8, p9, p10, p11, p12, p13, p14, p15]> {
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