Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.74 -> 1.75
---
Log message:
Teach tblgen to accept register source operands in patterns, e.g.
def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
"shl{b} {%cl, $dst|$dst, %CL}",
[(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.
---
Diffs of the changes: (+14 -0)
SelectionDAG.h | 14 ++++++++++++++
1 files changed, 14 insertions(+)
Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.74
llvm/include/llvm/CodeGen/SelectionDAG.h:1.75
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.74 Wed Nov 30 16:44:37 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h Wed Nov 30 18:18:45 2005
@@ -143,6 +143,20 @@
if (Flag.Val) Ops.push_back(Flag);
return getNode(ISD::CopyToReg, VTs, Ops);
}
+
+ // Similar to last getCopyToReg() except parameter Reg is a SDOperand
+ SDOperand getCopyToReg(SDOperand Chain, SDOperand Reg, SDOperand N,
+ SDOperand Flag) {
+ std::vector<MVT::ValueType> VTs;
+ VTs.push_back(MVT::Other);
+ VTs.push_back(MVT::Flag);
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Chain);
+ Ops.push_back(Reg);
+ Ops.push_back(N);
+ if (Flag.Val) Ops.push_back(Flag);
+ return getNode(ISD::CopyToReg, VTs, Ops);
+ }
SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT::ValueType VT) {
std::vector<MVT::ValueType> ResultTys;
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