Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.129 -> 1.130 PPCISelLowering.cpp updated: 1.42 -> 1.43 README.txt updated: 1.38 -> 1.39 --- Log message: Enable global address legalization, fixing a todo and allowing the removal of some code. This exposes the implicit load from the stubs to the DAG, allowing them to be optimized by the dag combiner. It also moves darwin specific stuff out of the isel into the legalizer, and allows more to be moved to the .td file. --- Diffs of the changes: (+2 -49) PPCISelDAGToDAG.cpp | 31 +------------------------------ PPCISelLowering.cpp | 2 +- README.txt | 18 ------------------ 3 files changed, 2 insertions(+), 49 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.129 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.130 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.129 Thu Nov 17 12:02:16 2005 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Nov 17 12:26:56 2005 @@ -428,20 +428,7 @@ } } - // Now check if we're dealing with a global, and whether or not we should emit - // an optimized load or store for statics. - if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) { - GlobalValue *GV = GN->getGlobal(); - if (!GV->hasWeakLinkage() && !GV->isExternal()) { - Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32); - if (PICEnabled) - Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), - Op1); - else - Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1); - return false; - } - } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) { + if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) { Op1 = getI32Imm(0); Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32); return false; @@ -907,22 +894,6 @@ } return CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, CPI); } -#if 1 - case ISD::GlobalAddress: { - GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal(); - SDOperand Tmp; - SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32); - if (PICEnabled) - Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA); - else - Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA); - - if (GV->hasWeakLinkage() || GV->isExternal()) - return CurDAG->getTargetNode(PPC::LWZ, MVT::i32, GA, Tmp); - else - return CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, GA); - } -#endif case ISD::FADD: { MVT::ValueType Ty = N->getValueType(0); if (!NoExcessFPPrecision) { // Match FMA ops Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.42 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.43 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.42 Thu Nov 17 11:51:38 2005 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Nov 17 12:26:56 2005 @@ -93,7 +93,7 @@ // We want to legalize GlobalAddress into the appropriate instructions to // materialize the address. - //setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); + setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { // They also have instructions for converting between i64 and fp. Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.38 llvm/lib/Target/PowerPC/README.txt:1.39 --- llvm/lib/Target/PowerPC/README.txt:1.38 Sat Nov 5 02:57:56 2005 +++ llvm/lib/Target/PowerPC/README.txt Thu Nov 17 12:26:56 2005 @@ -31,24 +31,6 @@ * Support 'update' load/store instructions. These are cracked on the G5, but are still a codesize win. -* Add a custom legalizer for the GlobalAddress node, to move the funky darwin - stub stuff from the instruction selector to the legalizer (exposing low-level - operations to the dag for optzn. For example, we want to codegen this: - - int A = 0; - void B() { A++; } - as: - lis r9,ha16(_A) - lwz r2,lo16(_A)(r9) - addi r2,r2,1 - stw r2,lo16(_A)(r9) - not: - lis r2, ha16(_A) - lwz r2, lo16(_A)(r2) - addi r2, r2, 1 - lis r3, ha16(_A) - stw r2, lo16(_A)(r3) - * should hint to the branch select pass that it doesn't need to print the second unconditional branch, so we don't end up with things like: b .LBBl42__2E_expand_function_8_674 ; loopentry.24 _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits