Changes in directory llvm/lib/Target/Alpha:
AlphaISelPattern.cpp updated: 1.179 -> 1.180
AlphaInstrFormats.td updated: 1.12 -> 1.13
AlphaInstrInfo.td updated: 1.71 -> 1.72
---
Log message:
continued readcyclecounter support
---
Diffs of the changes: (+16 -1)
AlphaISelPattern.cpp | 5 +++++
AlphaInstrFormats.td | 9 +++++++++
AlphaInstrInfo.td | 3 ++-
3 files changed, 16 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.179
llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.180
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.179 Thu Nov 10 10:59:55 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Fri Nov 11 10:46:18 2005
@@ -549,6 +549,11 @@
Node->dump();
assert(0 && "Node not handled!\n");
+ case ISD::READCYCLECOUNTER:
+ Select(N.getOperand(0)); //Select chain
+ BuildMI(BB, Alpha::RPCC, 1, Result).addReg(Alpha::R31);
+ return Result;
+
case ISD::CTPOP:
case ISD::CTTZ:
case ISD::CTLZ:
Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td
diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.12
llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.13
--- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.12 Wed Nov 9 13:17:08 2005
+++ llvm/lib/Target/Alpha/AlphaInstrFormats.td Fri Nov 11 10:46:18 2005
@@ -50,6 +50,15 @@
let Inst{20-16} = Rb;
let Inst{15-0} = disp;
}
+class MfcForm<bits<6> opcode, bits<16> fc, string asmstr>
+ : InstAlpha<opcode, (ops GPRC:$RA, GPRC:$RB), asmstr> {
+ bits<5> Ra;
+ bits<5> Rb;
+
+ let Inst{25-21} = Ra;
+ let Inst{20-16} = Rb;
+ let Inst{15-0} = fc;
+}
class MgForm<bits<6> opcode, string asmstr>
: InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB,
s16imm:$NUM), asmstr> {
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.71
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.72
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.71 Wed Nov 9 13:17:08 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Fri Nov 11 10:46:18 2005
@@ -465,6 +465,8 @@
def FBLT : FBForm<0x32, "fblt $RA,$DISP">; //Floating branch if < zero
def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero
+def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA">; //Read process cycle counter
+
//Basic Floating point ops
//Floats
@@ -558,7 +560,6 @@
//LDQ_L Mem 2B Load quadword locked
//LDQ_U Mem 0B Load unaligned quadword
//MB Mfc 18.4000 Memory barrier
-//RPCC Mfc 18.C000 Read process cycle counter
//STL_C Mem 2E Store longword conditional
//STQ_C Mem 2F Store quadword conditional
//STQ_U Mem 0F Store unaligned quadword
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