| Issue |
171473
|
| Summary |
[RISCV] Failure to merge memset (with gaps) to alloca
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
preames
|
Motivating example: https://godbolt.org/z/efv64oxoT
This is reduced from something in SPEC's perlbench regmatch, but was tweaked enough during reduction to likely be no longer representative. I thought the result was interesting on it's own.
If we have a stack allocation with multiple memsets used to initialize subsets of it, we can merge the memsets into one larger memset (by writing zeros to otherwise uninitialized space in the alloca). In this particular case, this would let us use a single VL predicated m8 store.
Specifically for RISCV, we also have the possibility of using a *masked* vse64.v if desired. That could be used to avoid the need to write to a memory location which wasn't otherwise written to, and thus could generalize the transform.
I think this hints at some RISCV specific opportunities for store merging in DAGCombine (or possibly elsewhere). Figuring out the costing of the masking vs multiple stores is unfortunately an interesting question.
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