| Issue |
161038
|
| Summary |
[RISCV] Reg allocation cause sub-optimal result
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
zzzhhhl
|
To allocate register for case below:
<img width="1900" height="968" alt="Image" src="" />
For line 14110, before allocating %40, all vrm8 register class is running out(except v0-v7). So when allocating %40, because of some strategy of greedy allocation, assuming it evict %30 ,and then assign v8m8(allocating to %30 before) to %40. and then push %30 into queue. But for %40, between def (line 14110 )and use(line 14112), there is no overlap for v8m8. so this spill/reload is redundant. For now, i add a pass to eliminate this scenario at post-ra stage.
Is there any better solution?
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