| Issue |
153812
|
| Summary |
SIFoldOperands generates unsupported instruction V_ADD_CO_U32_e32
|
| Labels |
backend:AMDGPU
|
| Assignees |
|
| Reporter |
jayfoad
|
With this test case:
```
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -start-before=si-fold-operands,1 %s -o - | FileCheck %s
--- |
@sym = external constant i32
define void @fn() { ret void }
...
---
name: fn
tracksRegLiveness: true
body: |
bb.0:
%0:vreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64 target-flags(amdgpu-abs64) @sym
%2:vgpr_32, %3:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 undef %1.sub0, undef %0.sub0, 0, implicit $exec
S_NOP 0, implicit %2
...
```
I get:
```sh
$ llc -mtriple=amdgcn -mcpu=gfx1200 -start-before=si-fold-operands,1 r.mir -o -
llc: /home/jayfoad2/git/llvm-project/llvm/include/llvm/MC/MCInstrInfo.h:65: const MCInstrDesc &llvm::MCInstrInfo::get(unsigned int) const: Assertion `Opcode < NumOpcodes && "Invalid opcode!"' failed.
```
I have not yet found a way to reproduce this from IR input, without making other changes to the compiler.
V_ADD_CO_U32_e32 is unsupported because V_ADD_CO_U32 is a VOP3-only instruction. I wonder if there is a better way to define this instruction, so that V_ADD_CO_U32_e32 does not exist in the first place. Failing that I think `SIFoldOperandsImpl::tryAddToFoldList` needs additional checks that the shrunk opcode is valid.
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