| Issue |
147662
|
| Summary |
[CIRCT][PyCDE] Segmentation fault when compiling a design with nested structs and FIFOs
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
AnZhong24
|
Warning: something is holding references to 1 MLIR ops
Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it):
0 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef7f332d8 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) + 40
1 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef7f2fbf5
2 libc.so.6 0x00007fbefba65520
3 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef801b590 mlir::Block::getParentOp() + 0
4 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef88e9cf4 circt::hw::HWDialect::materializeConstant(mlir::OpBuilder&, mlir::Attribute, mlir::Type, mlir::Location) + 116
5 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef8024d42 mlir::OpBuilder::tryFold(mlir::Operation*, llvm::SmallVectorImpl<mlir::Value>&, llvm::SmallVectorImpl<mlir::Operation*>*) + 1090
6 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef8eb4810
7 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef8eb4ed3 mlir::OperationConverter::convert(mlir::ConversionPatternRewriter&, mlir::Operation*) + 35
8 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef8eb6904 mlir::OperationConverter::convertOperations(llvm::ArrayRef<mlir::Operation*>) + 308
9 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef8eb8df3 mlir::applyPartialConversion(mlir::Operation*, mlir::ConversionTarget const&, mlir::FrozenRewritePatternSet const&, mlir::ConversionConfig) + 131
10 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef8be86a1
11 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef8135f91 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int) + 1249
12 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef81362e9 mlir::detail::OpToOpPassAdaptor::runPipeline(mlir::OpPassManager&, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int, mlir::PassInstrumentor*, mlir::PassInstrumentation::PipelineParentInfo const*) + 233
13 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef813666e
14 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef813683f
15 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef80e77ee
16 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef80e7f3b
17 libc.so.6 0x00007fbefbabcee8
18 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef80e7ebe
19 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef80e84cf
20 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef7f13fd2 llvm::StdThreadPool::processTasks(llvm::ThreadPoolTaskGroup*) + 530
21 libPyCDE_CIRCTPythonCAPI.so 0x00007fbef7f14dca
22 libc.so.6 0x00007fbefbab7ac3
23 libc.so.6 0x00007fbefbb49850
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Segmentation fault (core dumped)
**code:**
`
from pycde import Input, Output, Module, System, Clock, Reset
from pycde import generator, modparams
from pycde.constructs import Reg, Array, Mux,Wire
from pycde.types import Bits, SInt, UInt
from pycde.signals import Struct, BitsSignal
from pycde.dialects import comb,sv
@modparams
def FIFO(WIDTH: int, DEPTH_LOG2: int):
class FIFOImpl(Module):
module_name = f"fifo"
# Define inputs
clk = Clock()
rst_n = Input(Bits(1))
push_valid = Input(Bits(1))
push_data = Input(Bits(WIDTH))
pop_ready = Input(Bits(1))
# Define outputs
push_ready = Output(Bits(1))
pop_valid = Output(Bits(1))
pop_data = Output(Bits(WIDTH))
return FIFOImpl
@modparams
def TriggerCounter(WIDTH: int):
class TriggerCounterImpl(Module):
module_name = f"trigger_counter"
clk = Clock()
rst_n = Input(Bits(1))
delta = Input(Bits(WIDTH))
delta_ready = Output(Bits(1))
pop_ready = Input(Bits(1))
pop_valid = Output(Bits(1))
return TriggerCounterImpl
class record_ty(Struct):
is_odd: Bits(1)
payload:SInt(32)
def as_bits(self):
return BitsSignal.concat([self.is_odd,self.payload.as_bits()])
class Adder_834ec(Module):
clk = Clock()
rst = Reset()
executed = Output(Bits(1))
cycle_count = Input(UInt(64))
trigger_counter_pop_valid = Input(Bits(1))
a = Input(record_ty)
a_valid = Input(Bits(1))
a_pop_ready = Output(Bits(1))
b = Input(record_ty)
b_valid = Input(Bits(1))
b_pop_ready = Output(Bits(1))
expose_Adder_834ec_valid = Output(Bits(1))
valid_Adder_834ec_valid = Output(Bits(1))
expose_Adder_834ec__82621 = Output(SInt(32))
valid_Adder_834ec__82621 = Output(Bits(1))
expose_Adder_834ec__830fc = Output(SInt(32))
valid_Adder_834ec__830fc = Output(Bits(1))
expose_Adder_834ec_c = Output(SInt(32))
valid_Adder_834ec_c = Output(Bits(1))
@generator
def construct(self):
# a_valid = _834ec.a.valid()
a_valid = self.a_valid
# b_valid = _834ec.b.valid()
b_valid = self.b_valid
# a_b_valid = a_valid & b_valid
a_b_valid = ((a_valid & b_valid.as_bits()).as_bits()[0:1]).as_bits()
# side effect intrinsic.wait_until({'a_b_valid'})
# a = _834ec.a.pop()
a = self.a
# b = _834ec.b.pop()
b = self.b
# a_is_odd = a[(0:u1):(0:u1)]
a_is_odd = self.a.as_bits()[0:1]
# b_is_odd = b[(0:u1):(0:u1)]
b_is_odd = self.b.as_bits()[0:1]
# valid = a_is_odd & b_is_odd
valid = ((a_is_odd & b_is_odd.as_bits()).as_bits()[0:1]).as_bits()
# a_payload = a[(1:u1):(32:u6)]
a_payload = self.a.as_bits()[1:33]
# a_payload_cast = bitcast a_payload to i32
a_payload_cast = a_payload.as_sint()
# b_payload = b[(1:u1):(32:u6)]
b_payload = self.b.as_bits()[1:33]
# b_payload_cast = bitcast b_payload to i32
b_payload_cast = b_payload.as_sint()
# c = a_payload_cast + b_payload_cast
c = ((a_payload_cast + b_payload_cast).as_bits()[0:32]).as_sint()
# _830e9 = a[(1:u1):(32:u6)]
_830e9 = self.a.as_bits()[1:33]
# _82621 = bitcast _830e9 to i32
_82621 = _830e9.as_sint()
# _8e071 = b[(1:u1):(32:u6)]
_8e071 = self.b.as_bits()[1:33]
# _830fc = bitcast _8e071 to i32
_830fc = _8e071.as_sint()
# log('Adder: {} + {} = {}', _82621, _830fc, c)
executed_wire = self.trigger_counter_pop_valid & ((a_b_valid.as_bits() & self.trigger_counter_pop_valid))
# a = _834ec.a.pop()
self.a_pop_ready = executed_wire
# b = _834ec.b.pop()
self.b_pop_ready = executed_wire
# Expose: <assassyn.ir.expr.expr.Operand object at 0x7f9f4ea637a0>
self.expose_Adder_834ec_valid = valid
self.valid_Adder_834ec_valid = executed_wire
# Expose: _82621 = bitcast _830e9 to i32
self.expose_Adder_834ec__82621 = _82621
self.valid_Adder_834ec__82621 = executed_wire
# Expose: _830fc = bitcast _8e071 to i32
self.expose_Adder_834ec__830fc = _830fc
self.valid_Adder_834ec__830fc = executed_wire
# Expose: c = a_payload_cast + b_payload_cast
self.expose_Adder_834ec_c = c
self.valid_Adder_834ec_c = executed_wire
self.executed = executed_wire
class Driver(Module):
clk = Clock()
rst = Reset()
executed = Output(Bits(1))
cycle_count = Input(UInt(64))
trigger_counter_pop_valid = Input(Bits(1))
fifo_Adder_834ec_b_push_ready = Input(Bits(1))
fifo_Adder_834ec_a_push_ready = Input(Bits(1))
Adder_834ec_trigger_counter_delta_ready = Input(Bits(1))
Adder_834ec_a_push_valid = Output(Bits(1))
Adder_834ec_a_push_data = Output(record_ty)
Adder_834ec_b_push_valid = Output(Bits(1))
Adder_834ec_b_push_data = Output(record_ty)
Adder_834ec_trigger = Output(Bits(1))
array_8363c_payload = Input(Array(record_ty, 1))
array_8363c_ce = Output(Bits(1))
array_8363c_wdata = Output(record_ty)
@generator
def construct(self):
# value = array_8363c[(0:u0)]
value = self.array_8363c_payload[0]
# value_1 = value[(1:u1):(32:u6)]
value_1 = value.payload
# value_2 = bitcast value_1 to i32
value_2 = value_1.as_sint()
# is_odd = value_2[(0:u1):(0:u1)]
is_odd = value_2.as_bits()[0:1]
# new_value = value_2 + (1:i32)
new_value = ((value_2 + SInt(32)(1)).as_bits()[0:32]).as_sint()
# new_record = { new_value is_odd }
new_record = record_ty(is_odd=is_odd,payload = new_value)
# array_8363c[(0:u1)] = new_record
# _834ec.a.push(new_record) // handle = _836ba
# _834ec.b.push(new_record) // handle = _82671
# _836a5 = _834ec.bind([_836ba /* _834ec.a=new_record */, _82671 /* _834ec.b=new_record */])
# async_call _836a5
executed_wire = self.trigger_counter_pop_valid
# Expose: array_8363c[(0:u1)] = new_record
self.array_8363c_ce = executed_wire & (Bits(1)(1))
self.array_8363c_wdata = Mux(Bits(1)(1),new_record , new_record)
# Push logic for port: a
self.Adder_834ec_a_push_valid = executed_wire & ((Bits(1)(1))) & self.fifo_Adder_834ec_a_push_ready
self.Adder_834ec_a_push_data = new_record
# Push logic for port: b
self.Adder_834ec_b_push_valid = executed_wire & ((Bits(1)(1))) & self.fifo_Adder_834ec_b_push_ready
self.Adder_834ec_b_push_data = new_record
# async_call _836a5
self.Adder_834ec_trigger = executed_wire & (Bits(1)(1)) & self.Adder_834ec_trigger_counter_delta_ready
self.executed = executed_wire
class Top(Module):
clk = Clock()
rst = Reset()
global_cycle_count = Output(UInt(64))
@generator
def construct(self):
# A free-running counter for testbench control
cycle_count = Reg(UInt(64), clk=self.clk, rst=self.rst, rst_value=0)
cycle_count.assign( (cycle_count + UInt(64)(1)).as_bits()[0:64].as_uint() )
self.global_cycle_count = cycle_count
# --- Wires for FIFOs, Triggers, and Arrays ---
# Wires for FIFO connected to Adder_834ec.a
fifo_Adder_834ec_a_push_valid = Wire(Bits(1))
fifo_Adder_834ec_a_push_data = Wire(Bits(33))
fifo_Adder_834ec_a_push_ready = Wire(Bits(1))
fifo_Adder_834ec_a_pop_valid = Wire(Bits(1))
fifo_Adder_834ec_a_pop_data = Wire(Bits(33))
fifo_Adder_834ec_a_pop_ready = Wire(Bits(1))
# Wires for FIFO connected to Adder_834ec.b
fifo_Adder_834ec_b_push_valid = Wire(Bits(1))
fifo_Adder_834ec_b_push_data = Wire(Bits(33))
fifo_Adder_834ec_b_push_ready = Wire(Bits(1))
fifo_Adder_834ec_b_pop_valid = Wire(Bits(1))
fifo_Adder_834ec_b_pop_data = Wire(Bits(33))
fifo_Adder_834ec_b_pop_ready = Wire(Bits(1))
# Wires for Adder_834ec's TriggerCounter
Adder_834ec_trigger_counter_delta = Wire(Bits(8))
Adder_834ec_trigger_counter_delta_ready = Wire(Bits(1))
Adder_834ec_trigger_counter_pop_valid = Wire(Bits(1))
Adder_834ec_trigger_counter_pop_ready = Wire(Bits(1))
# Wires for Driver's TriggerCounter
Driver_trigger_counter_delta = Wire(Bits(8))
Driver_trigger_counter_delta_ready = Wire(Bits(1))
Driver_trigger_counter_pop_valid = Wire(Bits(1))
Driver_trigger_counter_pop_ready = Wire(Bits(1))
# Wires for Array array_8363c
array_8363c_ce = Wire(Bits(1))
array_8363c_wdata = Wire(record_ty)
reg_array_8363c = Reg(Array(record_ty, 1), clk=self.clk, rst=self.rst, rst_value= [record_ty(is_odd = Bits(1)(0),payload=SInt(32)(0))], ce=array_8363c_ce)
fifo_Adder_834ec_a_inst = FIFO(WIDTH=33, DEPTH_LOG2=2)(clk=self.clk, rst_n=~self.rst, push_valid=fifo_Adder_834ec_a_push_valid, push_data=fifo_Adder_834ec_a_push_data , pop_ready=fifo_Adder_834ec_a_pop_ready)
fifo_Adder_834ec_a_push_ready.assign(fifo_Adder_834ec_a_inst.push_ready)
fifo_Adder_834ec_a_pop_valid.assign(fifo_Adder_834ec_a_inst.pop_valid)
fifo_Adder_834ec_a_pop_data.assign(fifo_Adder_834ec_a_inst.pop_data)
fifo_Adder_834ec_b_inst = FIFO(WIDTH=33, DEPTH_LOG2=2)(clk=self.clk, rst_n=~self.rst, push_valid=fifo_Adder_834ec_b_push_valid, push_data=fifo_Adder_834ec_b_push_data, pop_ready=fifo_Adder_834ec_b_pop_ready)
fifo_Adder_834ec_b_push_ready.assign(fifo_Adder_834ec_b_inst.push_ready)
fifo_Adder_834ec_b_pop_valid.assign(fifo_Adder_834ec_b_inst.pop_valid)
fifo_Adder_834ec_b_pop_data.assign(fifo_Adder_834ec_b_inst.pop_data)
Adder_834ec_trigger_counter_inst = TriggerCounter(WIDTH=8)(clk=self.clk, rst_n=~self.rst, delta=Adder_834ec_trigger_counter_delta, pop_ready=Adder_834ec_trigger_counter_pop_ready)
Adder_834ec_trigger_counter_delta_ready.assign(Adder_834ec_trigger_counter_inst.delta_ready)
Adder_834ec_trigger_counter_pop_valid.assign(Adder_834ec_trigger_counter_inst.pop_valid)
Driver_trigger_counter_inst = TriggerCounter(WIDTH=8)(clk=self.clk, rst_n=~self.rst, delta=Driver_trigger_counter_delta, pop_ready=Driver_trigger_counter_pop_ready)
Driver_trigger_counter_delta_ready.assign(Driver_trigger_counter_inst.delta_ready)
Driver_trigger_counter_pop_valid.assign(Driver_trigger_counter_inst.pop_valid)
inst_Adder_834ec = Adder_834ec(clk=self.clk, rst=self.rst, trigger_counter_pop_valid=Adder_834ec_trigger_counter_pop_valid, cycle_count=cycle_count, a= record_ty(is_odd = fifo_Adder_834ec_a_pop_data[0:1].as_bits(),payload = fifo_Adder_834ec_a_pop_data[1:33].as_sint()), \
a_valid=fifo_Adder_834ec_a_pop_valid, b= record_ty(is_odd = fifo_Adder_834ec_b_pop_data[0:1].as_bits(),payload = fifo_Adder_834ec_b_pop_data[1:33].as_sint()), b_valid=fifo_Adder_834ec_b_pop_valid)
Adder_834ec_trigger_counter_pop_ready.assign(inst_Adder_834ec.executed)
fifo_Adder_834ec_a_pop_ready.assign(inst_Adder_834ec.a_pop_ready)
fifo_Adder_834ec_b_pop_ready.assign(inst_Adder_834ec.b_pop_ready)
# Instantiation for Driver
inst_Driver = Driver(clk=self.clk, rst=self.rst, trigger_counter_pop_valid=Driver_trigger_counter_pop_valid, cycle_count=cycle_count, array_8363c_payload=reg_array_8363c, fifo_Adder_834ec_b_push_ready=fifo_Adder_834ec_b_push_ready, fifo_Adder_834ec_a_push_ready=fifo_Adder_834ec_a_push_ready, Adder_834ec_trigger_counter_delta_ready=Adder_834ec_trigger_counter_delta_ready)
Driver_trigger_counter_pop_ready.assign(inst_Driver.executed)
fifo_Adder_834ec_b_push_valid.assign(inst_Driver.Adder_834ec_b_push_valid)
fifo_Adder_834ec_b_push_data.assign(inst_Driver.Adder_834ec_b_push_data.as_bits() )
fifo_Adder_834ec_a_push_valid.assign(inst_Driver.Adder_834ec_a_push_valid)
fifo_Adder_834ec_a_push_data.assign(inst_Driver.Adder_834ec_a_push_data.as_bits() )
# Connecting single writer for array array_8363c
array_8363c_ce.assign(inst_Driver.array_8363c_ce)
array_8363c_wdata.assign(inst_Driver.array_8363c_wdata)
reg_array_8363c.assign(Array(record_ty, 1)([array_8363c_wdata]))
Adder_834ec_trigger_counter_delta.assign(inst_Driver.Adder_834ec_trigger.as_uint().as_bits(8))
Driver_trigger_counter_delta.assign(Bits(8)(1))
system = System([Top], name="Top", output_directory="sv")
system.compile()
`
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