| Issue |
144289
|
| Summary |
RISC-V: RVV mask register allocation spill
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
my4ng
|
This example is derived from the RVV B.11 square root approximation example:
```llvm
define <vscale x 2 x i1> @test(<vscale x 2 x double> %0, <vscale x 2 x double> %1) {
entry:
%2 = tail call i64 @llvm.riscv.vsetvli.i64(i64 -1, i64 3, i64 1)
%3 = tail call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64.i64(<vscale x 2 x double> %0, double 0.000000e+00, i64 -1)
%4 = tail call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64.i64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, double 0.000000e+00, <vscale x 2 x i1> %3, i64 -1)
ret <vscale x 2 x i1> %4
}
```
The resulting assembly using llc trunk: [godbolt](https://godbolt.org/z/6n6s3d9r9)
```
test: # @test
fmv.d.x fa5, zero
vsetvli a0, zero, e64, m2, ta, mu
vmfne.vf v12, v8, fa5
vmv1r.v v0, v12
vmfne.vf v12, v10, fa5, v0.t
vmv1r.v v0, v12
ret
```
Here it moves the mask value into v0 twice, as when the vector multiplier is 4 or 8.
However, it behaves as expected when the vector multiplier is 1: [godbolt](https://godbolt.org/z/bKP76f1s1)
```
test: # @test
fmv.d.x fa5, zero
vsetvli a0, zero, e64, m1, ta, mu
vmfne.vf v0, v8, fa5
vmfne.vf v0, v9, fa5, v0.t
ret
```
This is a similar issue as #113489, where the mask register is unnecessarily moved, even though it does not need to be, as the specification states,
> The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), unless the destination vector register is being written with a mask value (e.g., compares) or the scalar result of a reduction.
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