Issue |
143825
|
Summary |
How to handle 64-bit data operations under RISCV32 in the backend
|
Labels |
new issue
|
Assignees |
|
Reporter |
muxiff
|
I am currently implementing a custom intrinsic instruction, which performs two i64 data operations under rv32 and returns an i64 type:
```
unsigned long long foo(unsigned long long a, unsigned long long b)
{
return __builtin_riscv_dkhm8(a, b);
}
```
The implemented partial code is as follows:
`clang/include/clang/Basic/BuiltinsRISCV.td`:
```
def dkhm8 : RISCVBuiltin<"uint64_t(uint64_t, uint64_t)">
```
`llvm/include/llvm/IR/IntrinsicsRISCVXxldsp.td`"
```
class GprGprPairIntrinsic
: Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
[IntrNoMem, IntrWillReturn, IntrSpeculatable]>;
def int_riscv_dkhm8 : GprGprPairIntrinsic;
```
IR can be generated normally:
```
; Function Attrs: noinline nounwind optnone
define dso_local i64 @foo(i64 noundef %a, i64 noundef %b) #0 {
entry:
%a.addr = alloca i64, align 8
%b.addr = alloca i64, align 8
store i64 %a, ptr %a.addr, align 8
store i64 %b, ptr %b.addr, align 8
%0 = load i64, ptr %a.addr, align 8
%1 = load i64, ptr %b.addr, align 8
%2 = call i64 @llvm.riscv.dkhm8(i64 %0, i64 %1)
ret i64 %2
}
```
However, the following problems were encountered in the instruction selection stage:
```
...
Continuing at 139534
Match failed at index 139538
Continuing at 141703
Continuing at 141704
fatal error: error in backend: Cannot select: t11: i64,ch = load<(dereferenceable load (s64) from %ir.a.addr)> t10, FrameIndex:i32<0>, undef:i32
t5: i32 = FrameIndex<0>
t7: i32 = undef
In function: foo
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script.
...
```
It seems that during the selectionDAG stage when handling the load node, under rv32, the backend fails to correctly match the load instruction for i64 data types. So, I wonder if it's due to the backend's restrictions or how I can adjust it myself?
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