| Issue |
141706
|
| Summary |
Make constant vector `<i64 poison, i64 -9223372036854775808>` able to reuse `<i64 0, i64 -9223372036854775808>`
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
Validark
|
Here's some LLVM IR:
```llvm
define dso_local <8 x i64> @bar(<8 x i64> %0) local_unnamed_addr {
Entry:
%1 = shufflevector <8 x i64> <i64 poison, i64 poison, i64 poison, i64 poison, i64 poison, i64 poison, i64 poison, i64 -9223372036854775808>, <8 x i64> %0, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
%2 = tail call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %0, <8 x i64> %1, <8 x i64> splat (i64 1))
%3 = xor <8 x i64> %2, <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 -9223372036854775808>
ret <8 x i64> %3
}
declare <8 x i64> @llvm.fshl.v8i64(<8 x i64>, <8 x i64>, <8 x i64>) #1
```
This currently gives (for znver5): [Godbolt link](https://llvm.godbo.lt/#g:!((g:!((g:!((h:codeEditor,i:(filename:'1',fontScale:14,fontUsePx:'0',j:1,lang:llvm,selection:(endColumn:71,endLineNumber:9,positionColumn:71,positionLineNumber:9,selectionStartColumn:71,selectionStartLineNumber:9,startColumn:71,startLineNumber:9),source:'define+dso_local+%3C8+x+i64%3E+@bar(%3C8+x+i64%3E+%250)+local_unnamed_addr+%7B%0AEntry:%0A++%251+%3D+shufflevector+%3C8+x+i64%3E+%3Ci64+poison,+i64+poison,+i64+poison,+i64+poison,+i64+poison,+i64+poison,+i64+poison,+i64+-9223372036854775808%3E,+%3C8+x+i64%3E+%250,+%3C8+x+i32%3E+%3Ci32+7,+i32+8,+i32+9,+i32+10,+i32+11,+i32+12,+i32+13,+i32+14%3e%0a++%252+%3d+tail+call+%3c8+x+i64%...@llvm.fshl.v8i64(%3C8+x+i64%3E+%250,+%3C8+x+i64%3E+%251,+%3C8+x+i64%3E+splat+(i64+1))%0A++%253+%3D+xor+%3C8+x+i64%3E+%252,+%3Ci64+0,+i64+0,+i64+0,+i64+0,+i64+0,+i64+0,+i64+0,+i64+-9223372036854775808%3e%0a++ret+%3c8+x+i64%3e+%253%0a%7d%0a%0adeclare+%3c8+x+i64%...@llvm.fshl.v8i64(%3C8+x+i64%3E,+%3C8+x+i64%3E,+%3C8+x+i64%3E)+%231'),l:'5',n:'0',o:'LLVM+IR+source+%231',t:'0')),k:50,l:'4',n:'0',o:'',s:0,t:'0'),(g:!((h:compiler,i:(compiler:llctrunk,filters:(b:'0',binary:'1',binaryObject:'1',commentOnly:'0',debugCalls:'1',demangle:'0',directives:'0',execute:'1',intel:'0',libraryCode:'0',trim:'1',verboseDemangling:'0'),flagsViewOpen:'1',fontScale:14,fontUsePx:'0',j:1,lang:llvm,libs:!(),options:'-mcpu%3Dznver5',overrides:!(),selection:(endColumn:25,endLineNumber:4,positionColumn:25,positionLineNumber:4,selectionStartColumn:25,selectionStartLineNumber:4,startColumn:25,startLineNumber:4),source:1),l:'5',n:'0',o:'+llc+(trunk)+(Editor+%231)',t:'0')),k:50,l:'4',n:'0',o:'',s:0,t:'0')),l:'2',n:'0',o:'',t:'0')),version:4)
```asm
.LCPI0_0:
.quad -9223372036854775808
.LCPI0_1:
.quad 0
.quad 0
.quad 0
.quad 0
.quad 0
.quad 0
.quad 0
.quad -9223372036854775808
bar:
valignq zmm1, zmm0, qword ptr [rip + .LCPI0_0]{1to8}, 7
vpshldq zmm0, zmm0, zmm1, 1
vpxorq zmm0, zmm0, zmmword ptr [rip + .LCPI0_1]
ret
```
Could be:
```asm
.LCPI0_0:
.quad 0
.quad 0
.quad 0
.quad 0
.quad 0
.quad 0
.quad 0
.quad -9223372036854775808
bar:
vmovdqa64 zmm2, zmmword ptr [rip + .LCPI0_0]
valignq zmm1, zmm0, zmm2, 7
vpshldq zmm0, zmm0, zmm1, 1
vpxorq zmm0, zmm0, zmm2
ret
```
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