| Issue |
140040
|
| Summary |
[AMDGPU] Form G_S/UBFX from uniform operations widened by RegBankSelect
|
| Labels |
new issue
|
| Assignees |
Pierre-vh
|
| Reporter |
Pierre-vh
|
We can widen uniform LSHR/AND operations from i16 to i32 in RegBankSelect, but then we cannot lower them to a s_bfe because we don't form G_S/UBFX in RegBankCombiner, and even if we did, we can't select uniform G_S/UBFX in AMDGPUInstructionSelector.
I think the easiest way to resolve this is to:
- Move S_BFE selection from RegBankSelect into AMDGPUInstructionSelector
- Make the BFX formation combine compatible with RB-selected MIR and add those combine to AMDGPURegBankSelector
The attached patch is a starting point for the first item. It doesn't handle the case where the offset/width are constants, so it emits too many instructions. We'd need an elegant way to get rid of the s_and/s_or/s_lshl if both operands are constant.
I'm not sure if that should be handled in the selection code, or if we should improve some peephole pass to constant fold trivial ops like that. I think the latter is more flexible and not that hard to implement.
Related to #64591
![]()
_______________________________________________
llvm-bugs mailing list
llvm-bugs@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs
