[llvm-bugs] [Bug 139284] [SPARC] Disassembler doesn't sign extend and aligns PC relative disponents.

[LLVM Bugs via llvm-bugs]

Issue	139284
Summary	[SPARC] Disassembler doesn't sign extend and aligns PC relative disponents.
Labels	new issue
Assignees
Reporter	Rot127

    According to the SparcV9 ISA the branch instructions with the format 2-4 have displacement immediate values which get sign extended:

![Image](https://github.com/user-attachments/assets/2c5ae2d8-fe57-49b6-8738-05e5680cb07e)

But the operand types for these displacement immediates never define a decoding method:

https://github.com/llvm/llvm-project/blob/865fb9c1a50f8b836a8c9ee6f4d1cbe7cce59fc3/llvm/lib/Target/Sparc/SparcInstrInfo.td#L224-L230

This leads to the bits being simply extracted and added as unsigned immediate operand to the `MCInst`.

The resulting branch instructions are not aligned, PC-relative or correctly sign extended values in the disassembler.

```c
echo "0x10, 0xbf, 0xff, 0xff" | llvm-mc --triple=sparcv9 --disassemble
	.text
	ba 4194303 // = 0x3FFFFF but should be 0xffffffff_fffffff0
```

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