| Issue | 133192 |
|---|---|
| Summary | [RISCV] Optimization Affected by mayRaiseFPException on FCVT_D_W[U] instructions |
| Labels | new issue |
| Assignees | |
| Reporter | circYuan |
Hi LLVM community, There appears to be an issue with MachineLICM optimization caused by the mayRaiseFPException flag being set for the FCVT_D_W and FCVT_D_WU instructions in RISCVInstrInfoD.td.
[Here is a reproducible example on Godbolt](https://godbolt.org/z/GYa7GKrbP) The fcvt.d.w instruction was hoisted out of the loop when compiled with llc-15, but it remains inside the loop when compiled with llc-trunc. According to the riscv-isa-release-1929d45-2025-03-26, fcvt.d.w[u] computes the exact value when converting from a 32-bit integer to a 64-bit floating-point value. However, the spec does not explicitly state whether these instructions may or may not raise floating-point exceptions. Here is the PR that originally introduced the mayRaiseFPException flag for these instructions: [Previous PR](https://reviews.llvm.org/D115540) I believe this flag was added based on the RISC-V ISA spec, but since the spec does not directly mention floating-point exceptions for these conversions, I would like to clarify whether the flag is truly necessary. For comparison, the fclass.s instruction is explicitly documented as not setting the floating-point exception flags. Conclusion The FCVT.D.W and FCVT.D.WU instructions may not need the mayRaiseFPException flag. However, I want to confirm whether removing this flag would result in any loss of information or if there are any corner cases where these instructions could indeed raise floating-point exceptions.
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