| Issue |
133141
|
| Summary |
[SPIR-V] structurizer/cf.switch.ifstmt.simple2.ll test case fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
VyacheslavLevytskyy
|
After https://github.com/llvm/llvm-project/pull/130605 structurizer/cf.switch.ifstmt.simple2.ll test case starts failing with the "PHI operand is not live-out from predecessor" diagnostic message. Machine Verifier finds the following problem after pre-legalizer step:
```
# After SPIRV pre legalizer
# Machine code for function main: IsSSA, TracksLiveness
bb.1.entry:
successors: %bb.3, %bb.2
%2:type(s64) = OpTypeFunction %1:type(s64)
%52:type(s64) = OpTypeInt 32, 0
%55:type(s64) = OpTypeBool
%62:type(s64) = OpTypeInt 64, 0
%1:type(s64) = OpTypeVoid
%0:iid(s64) = OpFunction %1:type(s64), 2, %2:type(s64)
OpName %0:iid(s64), 1852399981, 0
OpEntryPoint 5, %0:iid(s64), 1852399981, 0
%70:iid(s32) = G_CONSTANT i32 0
%4:iid(s32) = ASSIGN_TYPE %70:iid(s32), %52:type(s64)
%69:iid(s1) = G_CONSTANT i1 true
%6:iid(s1) = ASSIGN_TYPE %69:iid(s1), %55:type(s64)
%68:iid(s32) = G_CONSTANT i32 5
%10:iid(s32) = ASSIGN_TYPE %68:iid(s32), %52:type(s64)
%67:iid(s32) = G_CONSTANT i32 2
%14:iid(s32) = ASSIGN_TYPE %67:iid(s32), %52:type(s64)
%66:iid(s32) = G_CONSTANT i32 4
%20:iid(s32) = ASSIGN_TYPE %66:iid(s32), %52:type(s64)
%65:iid(s32) = G_CONSTANT i32 6
%23:iid(s32) = ASSIGN_TYPE %65:iid(s32), %52:type(s64)
%64:iid(s32) = G_CONSTANT i32 7
%25:iid(s32) = ASSIGN_TYPE %64:iid(s32), %52:type(s64)
%63:iid(p0) = G_CONSTANT i64 0
%27:iid(p0) = ASSIGN_TYPE %63:iid(p0), %62:type(s64)
%3:iid(s32) = COPY %4:iid(s32)
OpName %3:iid(s32), 845636978, 544040301, 1869376609, 1881170275, 1953393007, 0
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.selection.merge), %bb.27, 0
G_BRCOND %6:iid(s1), %bb.3
G_BR %bb.2
bb.2.unreachable:
; predecessors: %bb.1
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.unreachable)
bb.3.new.header:
; predecessors: %bb.1
successors: %bb.5, %bb.4
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.selection.merge), %bb.26, 0
G_BRCOND %6:iid(s1), %bb.5
G_BR %bb.4
bb.4.unreachable3:
; predecessors: %bb.3
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.unreachable)
bb.5.new.header2:
; predecessors: %bb.3
successors: %bb.7, %bb.6
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.selection.merge), %bb.22, 0
G_BRCOND %6:iid(s1), %bb.7
G_BR %bb.6
bb.6.unreachable5:
; predecessors: %bb.5
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.unreachable)
bb.7.new.header4:
; predecessors: %bb.5
successors: %bb.16(0x0e38e38e), %bb.15(0x0e38e38e), %bb.14(0x0e38e38e), %bb.13(0x0e38e38e), %bb.12(0x0e38e38e), %bb.11(0x0e38e38e), %bb.10(0x0e38e38e), %bb.9(0x0e38e38e), %bb.8(0x0e38e38e); %bb.16(11.11%), %bb.15(11.11%), %bb.14(11.11%), %bb.13(11.11%), %bb.12(11.11%), %bb.11(11.11%), %bb.10(11.11%), %bb.9(11.11%), %bb.8(11.11%)
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.selection.merge), %bb.17, 0
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.switch), %10:iid(s32), %bb.16, i32 1, %bb.15, i32 2, %bb.14, i32 3, %bb.13, i32 140, %bb.12, i32 4, %bb.11, i32 5, %bb.10, i32 6, %bb.9, i32 7, %bb.8
bb.8.entry.sw.bb12.i_crit_edge:
; predecessors: %bb.7
successors: %bb.17(0x80000000); %bb.17(100.00%)
G_BR %bb.17
bb.9.sw.bb11.i:
; predecessors: %bb.7
successors: %bb.17(0x80000000); %bb.17(100.00%)
G_BR %bb.17
bb.10.entry.sw.bb9.i_crit_edge1:
; predecessors: %bb.7
successors: %bb.17(0x80000000); %bb.17(100.00%)
G_BR %bb.17
bb.11.entry.sw.bb9.i_crit_edge:
; predecessors: %bb.7
successors: %bb.17(0x80000000); %bb.17(100.00%)
G_BR %bb.17
bb.12.sw.bb7.i:
; predecessors: %bb.7
successors: %bb.17(0x80000000); %bb.17(100.00%)
%61:iid(s32) = G_CONSTANT i32 140
%28:iid(s32) = ASSIGN_TYPE %61:iid(s32), %52:type(s64)
OpName %28:iid(s32), 946103393, 26926
G_BR %bb.17
bb.13.sw.bb5.i:
; predecessors: %bb.7
successors: %bb.17(0x80000000); %bb.17(100.00%)
%60:iid(s32) = G_CONSTANT i32 3
%29:iid(s32) = ASSIGN_TYPE %60:iid(s32), %52:type(s64)
OpName %29:iid(s32), 912548961, 26926
G_BR %bb.17
bb.14.entry.sw.bb3.i_crit_edge:
; predecessors: %bb.7
successors: %bb.17(0x80000000); %bb.17(100.00%)
G_BR %bb.17
bb.15.sw.bb.i:
; predecessors: %bb.7
successors: %bb.17(0x80000000); %bb.17(100.00%)
%59:iid(s32) = G_CONSTANT i32 1
%30:iid(s32) = ASSIGN_TYPE %59:iid(s32), %52:type(s64)
OpName %30:iid(s32), 778331233, 105
%58:iid(s32) = G_CONSTANT i32 200
%32:iid(s32) = ASSIGN_TYPE %58:iid(s32), %52:type(s64)
OpName %32:iid(s32), 845440097, 26926
G_BR %bb.17
bb.16.sw.default.i:
; predecessors: %bb.7
successors: %bb.17(0x80000000); %bb.17(100.00%)
G_BR %bb.17
bb.17.new.header4.new.exit:
; predecessors: %bb.8, %bb.9, %bb.10, %bb.11, %bb.12, %bb.13, %bb.14, %bb.15, %bb.16
successors: %bb.21(0x20000000), %bb.20(0x20000000), %bb.19(0x20000000), %bb.18(0x20000000); %bb.21(25.00%), %bb.20(25.00%), %bb.19(25.00%), %bb.18(25.00%)
%33:iid(s32) = G_PHI %4:iid(s32), %bb.16, %4:iid(s32), %bb.8, %4:iid(s32), %bb.9, %4:iid(s32), %bb.10, %4:iid(s32), %bb.11, %28:iid(s32), %bb.12, %29:iid(s32), %bb.13, %4:iid(s32), %bb.14, %30:iid(s32), %bb.15
%34:iid(s32) = G_PHI %4:iid(s32), %bb.16, %4:iid(s32), %bb.8, %4:iid(s32), %bb.9, %4:iid(s32), %bb.10, %4:iid(s32), %bb.11, %4:iid(s32), %bb.12, %4:iid(s32), %bb.13, %4:iid(s32), %bb.14, %32:iid(s32), %bb.15
%35:iid(s32) = G_PHI %14:iid(s32), %bb.16, %4:iid(s32), %bb.8, %4:iid(s32), %bb.9, %59:iid(s32), %bb.10, %59:iid(s32), %bb.11, %59:iid(s32), %bb.12, %14:iid(s32), %bb.13, %60:iid(s32), %bb.14, %60:iid(s32), %bb.15
OpName %35:iid(s32), 778528114, 48
OpName %34:iid(s32), 778645091, 48
OpName %33:iid(s32), 778645090, 48
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.selection.merge), %bb.21, 0
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.switch), %35:iid(s32), %bb.21, i32 1, %bb.20, i32 2, %bb.19, i32 3, %bb.18
bb.18.sw.bb3.i:
; predecessors: %bb.17
successors: %bb.21(0x80000000); %bb.21(100.00%)
%57:iid(s32) = nsw G_ADD %33:iid, %14:iid
%40:iid(s32) = nsw ASSIGN_TYPE %57:iid(s32), %52:type(s64)
OpName %40:iid(s32), 878994529, 26926
G_BR %bb.21
bb.19.new.header4.new.exit.new.src6:
; predecessors: %bb.17
successors: %bb.21(0x80000000); %bb.21(100.00%)
G_BR %bb.21
bb.20.new.header4.new.exit.new.src:
; predecessors: %bb.17
successors: %bb.21(0x80000000); %bb.21(100.00%)
G_BR %bb.21
bb.21.new.merge:
; predecessors: %bb.17, %bb.18, %bb.19, %bb.20
successors: %bb.22(0x80000000); %bb.22(100.00%)
%41:iid(s32) = G_PHI %33:iid(s32), %bb.17, %40:iid(s32), %bb.18, %33:iid(s32), %bb.19, %33:iid(s32), %bb.20
%42:iid(s32) = G_PHI %4:iid(s32), %bb.17, %14:iid(s32), %bb.18, %14:iid(s32), %bb.19, %59:iid(s32), %bb.20
OpName %42:iid(s32), 929523058, 12334
OpName %41:iid(s32), 778645090, 49
G_BR %bb.22
bb.22.new.header2.new.exit:
; predecessors: %bb.21
successors: %bb.25(0x2aaaaaaa), %bb.24(0x2aaaaaaa), %bb.23(0x2aaaaaaa); %bb.25(33.33%), %bb.24(33.33%), %bb.23(33.33%)
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.selection.merge), %bb.25, 0
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.switch), %42:iid(s32), %bb.25, i32 1, %bb.24, i32 2, %bb.23
bb.23.new.header2.new.exit.new.src:
; predecessors: %bb.22
successors: %bb.25(0x80000000); %bb.25(100.00%)
G_BR %bb.25
bb.24.sw.bb9.i:
; predecessors: %bb.22
successors: %bb.25(0x80000000); %bb.25(100.00%)
%56:iid(s32) = nsw G_ADD %41:iid, %10:iid
%46:iid(s32) = nsw ASSIGN_TYPE %56:iid(s32), %52:type(s64)
OpName %46:iid(s32), 828662881, 6893104
G_BR %bb.25
bb.25.new.merge9:
; predecessors: %bb.22, %bb.23, %bb.24
successors: %bb.26(0x80000000); %bb.26(100.00%)
%47:iid(s32) = G_PHI %41:iid(s32), %bb.22, %41:iid(s32), %bb.23, %46:iid(s32), %bb.24
%48:iid(s32) = G_PHI %4:iid(s32), %bb.22, %59:iid(s32), %bb.23, %59:iid(s32), %bb.24
OpName %48:iid(s32), 946300274, 12334
OpName %47:iid(s32), 778645090, 50
%49:iid(s1) = G_ICMP intpred(eq), %4:iid(s32), %48:iid
G_BR %bb.26
bb.26.new.header.new.exit:
; predecessors: %bb.25
successors: %bb.27(0x80000000); %bb.27(100.00%)
G_BR %bb.27
bb.27._ZL7processv.exit:
; predecessors: %bb.26
%54:iid(s32) = nsw G_ADD %4:iid, %47:iid
%50:iid(s32) = nsw ASSIGN_TYPE %54:iid(s32), %52:type(s64)
OpName %50:iid(s32), 828662881, 6893107
%53:iid(s32) = nsw G_ADD %50:iid, %34:iid
%51:iid(s32) = nsw ASSIGN_TYPE %53:iid(s32), %52:type(s64)
OpName %51:iid(s32), 828662881, 6893108
OpReturn
# End machine code for function main.
*** Bad machine code: PHI operand is not live-out from predecessor ***
- function: main
- basic block: %bb.17 new.header4.new.exit (0x5c98edd11210)
- instruction: %35:iid(s32) = G_PHI %14:iid(s32), %bb.16, %4:iid(s32), %bb.8, %4:iid(s32), %bb.9, %59:iid(s32), %bb.10, %59:iid(s32), %bb.11, %59:iid(s32), %bb.12, %14:iid(s32), %bb.13, %60:iid(s32), %bb.14, %60:iid(s32), %bb.15
- operand 7: %59:iid
*** Bad machine code: PHI operand is not live-out from predecessor ***
- function: main
- basic block: %bb.17 new.header4.new.exit (0x5c98edd11210)
- instruction: %35:iid(s32) = G_PHI %14:iid(s32), %bb.16, %4:iid(s32), %bb.8, %4:iid(s32), %bb.9, %59:iid(s32), %bb.10, %59:iid(s32), %bb.11, %59:iid(s32), %bb.12, %14:iid(s32), %bb.13, %60:iid(s32), %bb.14, %60:iid(s32), %bb.15
- operand 9: %59:iid
*** Bad machine code: PHI operand is not live-out from predecessor ***
- function: main
- basic block: %bb.17 new.header4.new.exit (0x5c98edd11210)
- instruction: %35:iid(s32) = G_PHI %14:iid(s32), %bb.16, %4:iid(s32), %bb.8, %4:iid(s32), %bb.9, %59:iid(s32), %bb.10, %59:iid(s32), %bb.11, %59:iid(s32), %bb.12, %14:iid(s32), %bb.13, %60:iid(s32), %bb.14, %60:iid(s32), %bb.15
- operand 11: %59:iid
*** Bad machine code: PHI operand is not live-out from predecessor ***
- function: main
- basic block: %bb.17 new.header4.new.exit (0x5c98edd11210)
- instruction: %35:iid(s32) = G_PHI %14:iid(s32), %bb.16, %4:iid(s32), %bb.8, %4:iid(s32), %bb.9, %59:iid(s32), %bb.10, %59:iid(s32), %bb.11, %59:iid(s32), %bb.12, %14:iid(s32), %bb.13, %60:iid(s32), %bb.14, %60:iid(s32), %bb.15
- operand 15: %60:iid
*** Bad machine code: PHI operand is not live-out from predecessor ***
- function: main
- basic block: %bb.17 new.header4.new.exit (0x5c98edd11210)
- instruction: %35:iid(s32) = G_PHI %14:iid(s32), %bb.16, %4:iid(s32), %bb.8, %4:iid(s32), %bb.9, %59:iid(s32), %bb.10, %59:iid(s32), %bb.11, %59:iid(s32), %bb.12, %14:iid(s32), %bb.13, %60:iid(s32), %bb.14, %60:iid(s32), %bb.15
- operand 17: %60:iid
*** Bad machine code: Virtual register defs don't dominate all uses. ***
- function: main
- v. register: %59
*** Bad machine code: Virtual register defs don't dominate all uses. ***
- function: main
- v. register: %60
```
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