| Issue |
133048
|
| Summary |
[CodeGen][ARM] Missed optimizated load store pair instruction combine
|
| Labels |
backend:ARM,
llvm:optimizations,
missed-optimization
|
| Assignees |
|
| Reporter |
hstk30-hw
|
https://godbolt.org/z/db17KEWK1
```
typedef struct tagContext {
unsigned long long int a;
unsigned long long int b;
unsigned long long int c;
} Context ;
void test(Context *context) {
context->a = 0;
context->b = 0;
context->c = 0;
}
```
GCC output:
```
test:
movs r2, #0
movs r3, #0
strd r2, [r0]
strd r2, [r0, #8]
strd r2, [r0, #16]
bx lr
```
llvm output:
```
test:
mov r1, #0
str r1, [r0]
str r1, [r0, #4]
str r1, [r0, #8]
str r1, [r0, #12]
str r1, [r0, #16]
str r1, [r0, #20]
bx lr
```
ARMLoadStoreOptimizer Pass have Pre/post register allocation
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