| Issue |
132667
|
| Summary |
[RISC-V] Is RISC-V vector LMUL being considered as a factor for instruction scheduling in MachineScheduler implementation?
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
zhongchengyong
|
The RVV instruction occupy the function unit more than one cycle when LMUL > 1, but as far as I know from the current `MachineScheduler.cpp` implementation, it seems that the LMUL is NOT considered as a factor for instruction scheduling.
Thanks!
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