| Issue |
132180
|
| Summary |
[RISCV][EVL] Improve AnyOf reduction codegen
|
| Labels |
backend:RISC-V,
vectorizers
|
| Assignees |
|
| Reporter |
lukel97
|
On RISC-V, an AnyOf reduction is vectorized quite poorly with EVL tail folding:
```c
int f(int *x, int y, int n) {
int z = 0;
for (int i = 0; i < n; i++)
if (x[i] == y)
z = 1;
return z;
}
```
```asm
.LBB0_2: # %vector.body
# =>This Inner Loop Header: Depth=1
sub t0, a2, a3
sh2add a6, a3, a0
vsetvli t1, t0, e8, mf2, ta, ma
vsetvli a4, zero, e64, m4, ta, ma
vmv.v.x v16, t1
vmsleu.vv v9, v16, v12
vsetvli zero, t0, e32, m2, ta, ma
vle32.v v10, (a6)
sub a5, a5, a7
vsetvli a4, zero, e64, m4, ta, ma
vmsltu.vx v16, v12, t1
vmand.mm v9, v8, v9
vsetvli zero, zero, e32, m2, ta, ma
vmseq.vx v17, v10, a1
vmor.mm v8, v8, v17
vmand.mm v8, v8, v16
vmor.mm v8, v8, v9
add a3, a3, t1
bnez a5, .LBB0_2
# %bb.3: # %middle.block
vcpop.m a0, v8
snez a0, a0
ret
```
Compare this to the non-EVL tail folded version:
```asm
.LBB0_5: # %vector.body
# =>This Inner Loop Header: Depth=1
vl2re32.v v10, (a3)
add a3, a3, a4
vsetvli zero, zero, e32, m2, ta, ma
vmseq.vx v9, v10, a1
vmor.mm v8, v8, v9
bne a3, a5, .LBB0_5
# %bb.6: # %middle.block
vcpop.m a3, v8
# ...
```
The issue is due to the i1 vp.merge used having poor lowering, in turn due to the lack of tail preserving mask instructions in the RISC-V ISA.
A better lowering is likely to widen this to an i8 vector:
```asm
vsetvli a5, zero, e8, m1, ta, ma
vmv.v.i v9, 0
loop:
vsetvli a5, a7, e32, m1, ta, ma
vle32.v v8, (a0)
add a0, a0, a5
vmseq.vx v0, v8, zero
vsetvli zero, zero, e8, mf4, ta, ma
vmerge.vim v10, v9, 1, v0
vor.vv v11, v11, v10
sub a7, a7, a5
bnez a7, loop
exit:
vmsne.vi v10, v11, 0
vcpop.m a1, v10
```
Performing this as an in-loop reduction was also discussed in #131830, but it's likely not as profitable as the widened out-of-loop reduction.
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