| Issue |
131879
|
| Summary |
[RISCV] RVV with inline assembly
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
mp-17
|
Hello,
Is it possible to compile .c files with clang targeting `-march=rv64gcv` without letting the compiler insert any vector instructions in addition to the ones written in inline assembly?
Use case: I have plenty of code that uses inline assembly to set precise sequences of vector instructions (this is also useful for verification), and I use it with .c code.
With older versions of clang (v16), `-fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0` did the job. Everything compiled as my RVV inline assembly was not even there, except for correct variable handling in my extended asm.
Now, with clang v20, I am not sure this is enough/correct anymore. I compiled my code with these options, but the compiled program looks messed up. After every vector instruction, I see something like this:
```
8000201c: 0c0572d7 vsetvli t0, a0, e8, m1, ta, ma
80002020: 0b358513 addi a0, a1, 0xb3
80002024: 00e54583 lbu a1, 0xe(a0)
80002028: 00b10723 sb a1, 0xe(sp)
8000202c: 00c54583 lbu a1, 0xc(a0)
80002030: 00b10623 sb a1, 0xc(sp)
80002034: 00a54583 lbu a1, 0xa(a0)
80002038: 00b10523 sb a1, 0xa(sp)
8000203c: 00854583 lbu a1, 0x8(a0)
80002040: 00b10423 sb a1, 0x8(sp)
80002044: 00654583 lbu a1, 0x6(a0)
80002048: 00b10323 sb a1, 0x6(sp)
8000204c: 00454583 lbu a1, 0x4(a0)
80002050: 00b10223 sb a1, 0x4(sp)
80002054: 00254583 lbu a1, 0x2(a0)
80002058: 00b10123 sb a1, 0x2(sp)
8000205c: 00054583 lbu a1, 0x0(a0)
```
Moreover, the program's functionality is compromised.
Thanks a lot for the help.
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