| Issue |
130075
|
| Summary |
MachineVerifier does not diagnose REG_SEQUENCE with overlapping input operands
|
| Labels |
llvm:codegen,
llvm:regalloc,
accepts-invalid
|
| Assignees |
|
| Reporter |
arsenm
|
The verifier does not reject cases where a reg_sequence specifies multiple values for a subregister index
```
# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s
# Inputs to a reg sequence should be unique and not set overlapping
# inputs
---
name: overlapping_reg_sequence_inputs
tracksRegLiveness: true
body: |
bb.0:
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub0
%3:vreg_64 = IMPLICIT_DEF
%4:vreg_128 = REG_SEQUENCE %0, %subreg.sub0_sub1, %1, %subreg.sub0
...
```
This should error on both of these reg_sequences. In %2, the same subregister index is repeated twice so the input to use for sub0 is ambiguous.
%4 should also be an error, %subreg.sub0 overlaps with %subreg.sub0
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