| Issue |
130245
|
| Summary |
AMDGPU misses general case to match s_bitset instructions
|
| Labels |
backend:AMDGPU,
missed-optimization
|
| Assignees |
|
| Reporter |
arsenm
|
We currently do not try very hard to make use of s_bitset0_b32/s_bitset0_b64 or s_bitset1_b32/s_bitset1_b64
```
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s
; s_lshl_b32 s1, 1, s1
; s_or_b32 s0, s0, s1
; This can emit s_bitset1_b32
define amdgpu_ps i32 @s_bitset1_b32(i32 inreg %src0, i32 inreg %bit.index) {
%set.bit.at.index = shl i32 1, %bit.index
%or = or i32 %src0, %set.bit.at.index
ret i32 %or
}
; s_lshl_b32 s1, 1, s1
; s_andn2_b32 s0, s0, s1
; This can emit s_bitset0_b32
define amdgpu_ps i32 @s_bitset0_b32(i32 inreg %src0, i32 inreg %bit.index) {
%set.bit.at.index = shl i32 1, %bit.index
%other.bits = xor i32 %set.bit.at.index, -1
%and = and i32 %src0, %other.bits
ret i32 %and
}
```
We only recognize and / or with a constant in SIShrinkInstructions. We should be able to recognize cases with a bit set to a variable index
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