| Issue |
128468
|
| Summary |
[RISCV] Redundant sext can not be eliminated in sext removal pass.
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
Ruhung
|
RISCV Backend generates more sext in this case after we select ADDI instead of ORI for OR (https://reviews.llvm.org/D140674) when there are no common bits between them in instruction selection phase. During the sext removal optimization phase, ADDI and ORI behave differently: When the DU chain meets an ORI instruction, it continues searching for the next instruction since ORI can propagate sign-extended values. However, when it meets ADDI, it first checks whether the instruction's users ignore the upper 32 bits to determine if it can be replaced with ADDIW, and this check failed in the case. I think maybe we can also check whether ADDI can propagate the signed extended values in certain cases.
https://godbolt.org/z/41Px3e64c
![]()
_______________________________________________
llvm-bugs mailing list
llvm-bugs@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bugs
